Error 12007 top level design entity counter is undefined

Error 12007 top level design entity is undefined quartus

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Error 12007.

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I have been on this error for quite a while now, I have read all the other threads but i haven’t seen a way to solve this issue.

The code is attached.

Info: Running Quartus Prime Analysis & Synthesis

Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition

Info: Processing started: Fri May 27 14:20:43 2016

Info: Command: quartus_map —read_settings_files=on —write_settings_files=off procpld -c procpldtop

Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected

Error (12007): Top-level design entity «procpldtop» is undefined

Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

Error: Peak virtual memory: 739 megabytes

Error: Processing ended: Fri May 27 14:20:57 2016

Error: Elapsed time: 00:00:14

Error: Total CPU time (on all processors): 00:00:23

Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 0 warnings

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Error 12007 top level design entity is undefined quartus

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Error 12007.

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I have been on this error for quite a while now, I have read all the other threads but i haven’t seen a way to solve this issue.

The code is attached.

Info: Running Quartus Prime Analysis & Synthesis

Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition

Info: Processing started: Fri May 27 14:20:43 2016

Info: Command: quartus_map —read_settings_files=on —write_settings_files=off procpld -c procpldtop

Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected

Error (12007): Top-level design entity «procpldtop» is undefined

Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

Error: Peak virtual memory: 739 megabytes

Error: Processing ended: Fri May 27 14:20:57 2016

Error: Elapsed time: 00:00:14

Error: Total CPU time (on all processors): 00:00:23

Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 0 warnings

Источник

Ошибка Altera Quartus (12007): объект проектирования верхнего уровня «alt_ex_1» не определен.

Я просмотрел все предыдущие вопросы, и, похоже, ни у кого нет такой простой проблемы, как у меня. Также я искал в Интернете и не нашел решения.

Я новичок в VHDL и пытаюсь скомпилировать простой пример, предоставленный Altera, который выглядит следующим образом:

Я выполнил шаги создания проекта в руководстве по Altera , но когда я пытаюсь скомпилировать проект, я получаю сообщение об ошибке:

В главе Starting a New Project вас попросили назвать ваш проект light . Мне кажется, что вы неправильно выполнили этот шаг и назвали свой проект alt_ex_1 . Вот почему вы получаете ошибку 12007, поскольку компилятор не знает, что является объектом верхнего уровня в вашей разработке.

Чтобы решить эту проблему, вы можете:

1. Измените назначение сущности верхнего уровня в Assignments -> Device -> General .
2. Установите свой модуль как верхний объект через Project Navigator ( Files -> Set as top-level entity ).

Кстати 1 , 2 , 3 , . — у всех примерно одна и та же проблема.

Моя проблема была связана с компилятором кода Verilog. Но когда я ищу проблему, я всегда видел этот вопрос. Поэтому я решил добавить свое решение, чтобы направлять других. Мне потребовалось много времени, чтобы найти решение. вот что я сделал для решения проблемы. Просто выполните следующие действия (Quartus II 14.0.0); Assignments -> Settings -> Top-Level Entity -> Select your module

Просто наведите указатель мыши на имя файла на панели навигатора проекта и щелкните правой кнопкой, а затем нажмите (установить как объект верхнего уровня). Выполнено.

Краткий ответ

Сообщение об ошибке далеко не тривиально для понимания, но окольным путем оно говорит о том, что не так. Вы (вероятно) используете alt_ex_1.vhd в качестве имени своего файла дизайна.
В Altera Quartus имя файла должно совпадать с именем (верхнего уровня), entity объявленным в коде проекта VHDL.
Что вам нужно сделать, так это изменить имя файла с alt_ex_1.vhd на light.vhd .
Для простоты создайте новый проект с именем light вместо alt_ex_1 .

Подробный ответ

Воспроизвести ошибку просто. Вот что я сделал. 1

После запуска Quartus Prime Lite Edition щелкните File > New Project Wizard. .
Если вы видите Введение , щелкните Next > . Выберите рабочий каталог.
В качестве названия проекта укажите alt_ex_1 . Next > Дважды щелкните, а затем Finish .
Создайте файл дизайна: File > New. .
Под Design Files выберите VHDL File , затем OK .
Далее File > Save As. . Введите или вставьте alt_ex_1.vhd и щелкните Save .
Вставьте код:

и снова сохраните файл.

Компиляция с Processing > Start > Start Analysis & Synthesis — или нажмите Ctrl + K . В окне сообщения отображается ошибка:

Чтобы избавиться от надоедливой ошибки, удалите все файлы, которые были созданы в рабочем каталоге, а затем начните все сначала. Следуйте инструкции, что и выше, но на этот раз необходимо заменить каждое вхождение alt_ex_1 с light .

В окне сообщения ожидайте увидеть что-то вроде:

как одна из последних строк.

1 Использование Altera / Intel Quartus Lite 18.1 в Windows 10, но версия, скорее всего, не важна.

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Error 12007 top level design entity is undefined quartus

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• Re: Error: top level design entity » » is undefined

Error: top level design entity » » is undefined

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we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity » file name» is undefined.

We are even taking care of the case sensitivity.

Our file name, new created project name and entity name in the code are all same.

Plz help us regarding this.

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I think this relates to th OPs problem. There seems to be a typo in the supplied file from Altera as part of DE2_tutorialsdesign_files data set has the top level entity/arch named addersubtractor2 in addersubtractor.vhd, it should of course be addersubtractor the file is marked (C) 2005 Altera Corporation.

ENTITY addersubtractor2 IS

GENERIC ( n : INTEGER := 16 ) ;

PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Clock, Reset, Sel, AddSub : IN STD_LOGIC ;

Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Overflow: OUT STD_LOGIC ) ;

ARCHITECTURE Behavior OF addersubtractor2 IS.

This section of the file should read (as it did in 8.0sp1 supplied files):

ENTITY addersubtractor IS

GENERIC ( n : INTEGER := 16 ) ;

PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Clock, Reset, Sel, AddSub : IN STD_LOGIC ;

Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Overflow: OUT STD_LOGIC ) ;

ARCHITECTURE Behavior OF addersubtractor IS.

This file is marked — (C) 2004 Altera Corporation. All rights reserved.

Looks like a typo possibly, but if you change the top level entity and architecture to match as shown it will compile ok. Not helpful for beginners!

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Hello, guys, thanks for all your efforts,

I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)

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I strongly suggest to check the spell of the name of your entity.

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I solved this in Quartus II 11.0 by going Assignments > Settings > General and making my Top-level entity the name of my top level Verilog module (not its filename).

e.g. for a file named example.v

module circuit (output f, input x,y,z);

make the Top-level entity «circuit» not «example»

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save yourself some pain when changing top level entities (for debug) and match your file and module name

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Hello, guys, thanks for all your efforts,

I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)

your post solved my lot of problems, thank you very much. You made me understand a very important concept.

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Resurrecting an old thread here, but I just had this problem and this thread came up top of a google search. I’ve been using Quartus for 8 months now but have always been copying existing projects, but I recently tried a new project and it was a bit tricky so I have gone through every step and written it up below. Even in this simple led blink program there are 3 places that the project name is mentioned and it must match all these to avoid a «top level design entity» error.

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Error 12007 top level design entity is undefined quartus

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• Re: Error: top level design entity » » is undefined

Error: top level design entity » » is undefined

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we have problem in compiling VHDL code in Quartus II software. Every time we compile it shows the Error:top level design entity » file name» is undefined.

We are even taking care of the case sensitivity.

Our file name, new created project name and entity name in the code are all same.

Plz help us regarding this.

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I think this relates to th OPs problem. There seems to be a typo in the supplied file from Altera as part of DE2_tutorialsdesign_files data set has the top level entity/arch named addersubtractor2 in addersubtractor.vhd, it should of course be addersubtractor the file is marked (C) 2005 Altera Corporation.

ENTITY addersubtractor2 IS

GENERIC ( n : INTEGER := 16 ) ;

PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Clock, Reset, Sel, AddSub : IN STD_LOGIC ;

Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Overflow: OUT STD_LOGIC ) ;

ARCHITECTURE Behavior OF addersubtractor2 IS.

This section of the file should read (as it did in 8.0sp1 supplied files):

ENTITY addersubtractor IS

GENERIC ( n : INTEGER := 16 ) ;

PORT ( A, B : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Clock, Reset, Sel, AddSub : IN STD_LOGIC ;

Z : BUFFER STD_LOGIC_VECTOR(n-1 DOWNTO 0) ;

Overflow: OUT STD_LOGIC ) ;

ARCHITECTURE Behavior OF addersubtractor IS.

This file is marked — (C) 2004 Altera Corporation. All rights reserved.

Looks like a typo possibly, but if you change the top level entity and architecture to match as shown it will compile ok. Not helpful for beginners!

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Hello, guys, thanks for all your efforts,

I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)

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I strongly suggest to check the spell of the name of your entity.

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I solved this in Quartus II 11.0 by going Assignments > Settings > General and making my Top-level entity the name of my top level Verilog module (not its filename).

e.g. for a file named example.v

module circuit (output f, input x,y,z);

make the Top-level entity «circuit» not «example»

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save yourself some pain when changing top level entities (for debug) and match your file and module name

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Hello, guys, thanks for all your efforts,

I encountered the same problem and solved it just now. It was due to the typo of my top level design entity name. A stupid mistake =)

your post solved my lot of problems, thank you very much. You made me understand a very important concept.

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Resurrecting an old thread here, but I just had this problem and this thread came up top of a google search. I’ve been using Quartus for 8 months now but have always been copying existing projects, but I recently tried a new project and it was a bit tricky so I have gone through every step and written it up below. Even in this simple led blink program there are 3 places that the project name is mentioned and it must match all these to avoid a «top level design entity» error.

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Время создания страницы: 0.395 секунд

Доброго времени суток! Пытаюсь написать суммирующий счетчик по модулю 10, но в процессе компиляции выскакивает ошибка:

Вот то, что предшествует ошибке :

Способ устранения методом Project/Set As Top Level Entity -реакции не последовало никакой
Вот, собственно, листинг:

library IEEE;
use ieee.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity counter10 is
port (c: in std_logic;
Q: out std_logic_vector(9 downto 0));
end counter10;
architecture arh1 of counter10 is
signal cnt: std_logic_vector (9 downto 0);
begin
process (c)
begin
if rising_edge(c) then
cnt <= cnt+'1';
end if;
end process;
Q <= cnt;
end arh1;

P.S на пометку код в С# прошу внимания не обращать, код в VHDL, не нашел для сеего контейнер. Программа, в которой работаю : Quartus II 8.1

library ieee;
use ieee.std_logic_1164.all;

entity light is
port(x1, x2: in std_logic;
          f: out std_logic);
end light;

architecture LogicFunction of light is
begin
    f <= (x1 and not x2) or (not x1  and x2);
end LogicFunction;

Error (12007): Top-level design entity "alt_ex_1" is undefined

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Лучший ответ

Error (12007): Top-level design entity "alt_ex_1" is undefined

library ieee;
use ieee.std_logic_1164.all;

entity light is
port(x1, x2: in std_logic;
          f: out std_logic);
end light;

architecture LogicFunction of light is
begin
    f <= (x1 and not x2) or (not x1  and x2);
end LogicFunction;

12007 Top-level design entity "alt_ex_1" is undefined

Quartus Analysis & Synthesis was successful. 0 errors, 1 warning