Error amplifier compensation

Compensation for Error Caused by Limited Gain-Bandwidth of Operational Amplifiers in Low-pass Filters

An operational amplifier has the internal compensation circuit for stability which limits its working bandwidth. Frequency response of the compensated Op Amp has slope of −6 dB/octave or −20 dB/decade. Unity gain frequency defines the bandwidth where the Op Amp is able to amplify a signal. If we multiply the gain and frequency at any point, the result is the same, allowing us to use this parameter to select the appropriate Op Amp. It is called Gain-Bandwidth Product, GBW or GBP. The limited open-loop gain introduces a closed-loop gain and phase error.

But we want to optimize our circuits, right?

Closed-loop gain of the Non-Inverting and Inverting Amplifier

The closed-loop gain of the non-inverting amplifier is:

and for the inverting amplifier:

A is the open-loop gain;
β is the feedback fraction.

Let’s calculate, for example, an inverting amplifier with desired gain of 1 when , :

But to make a real Op Amp stable, A is frequency dependent and there is a phase shift, how you can see in the picture below.

Frequency response of the compensated Op Amp without a feedback network

The inverting amplifier with ideal and compensated Op Amp.

The figure shows the difference between the ideal and compensated Op Amp with GBW = 1 MHz. You can see that the cyan line of the compensated Op Amp is always below the yellow line showing its open-loop gain and there must be some margin.

However, the simulator shows that gain at 1 МГц is not -9.55 dB, but about -7 dB due to a phase shift at the output.

The closed-loop gain error versus gain margin for the non-inverting amplifier looks likes that:

Closed-loop gain error vs Gain margin of the non-inverting amplifier.

Error compensation for 2-nd order low-pass filter

This equation is usually used to compute the GBW of an Op Amp:

Q is the quality factor of the filter;
G is the specified gain;
F3 is the cutoff frequency at -3 dB;
100 is the gain margin.

Why? A low-pass filter with has a peak and we need to multiply the gain with this peak value to account it. The peak value is:

The most of used filters are low-pass filters for ADCs and DACs. So even for an LPF with 150 kHz an Op Amp with GBW of 15 MHz is desirable.

Texas Instruments’ engineers shared a method to reduce the requirement in [1][2].
Let’s try to figure out how to use their equations in practice.

Multiple FeedBack LPF

2-nd order MFB LPF

The required GBW is:

Let’s try to use an Op Amp with GBW of 1 MHz.

Add R4 in series with C2:

And finally enter the values into a simulator:

Error compensation for 2-nd order MFB LPF

The top circuit and green color on the charts: the ideal amplifier.
The middle circuit and cyan color on the charts: the Op Amp with GBW of 1 MHz.
The bottom circuit and yellow color on the charts: the Op Amp with GBW of 1 MHz and with the error compensation.

When R3 is too low, the R3’ value may be negative. In such cases you should recalculate the filter with a greater R3 value.

Sallen-Key LPF

2-nd order Sallen-Key LPF

The required GBW is:

Let’s try to use an Op Amp with GBW of 1 MHz.

Add R5 in series with C1:

And finally enter the values into a simulator:

Error compensation for 2-nd order Sallen-Key LPF

The top circuit and green color on the charts: the ideal amplifier.
The middle circuit and cyan color on the charts: the Op Amp with GBW of 1 MHz.
The bottom circuit and yellow color on the charts: the Op Amp with GBW of 1 MHz and with the error compensation.

Error compensation for Type II compensation network with Op Amp

Let’s try to apply the same method to the Type II compensation network with Op Amp used in switching-mode power supplies.

Consider a Type II circuit with parameters: the zero at 2 kHz, the pole at 300 kHz, the middle gain is 0 dB.

Type 2 compensation with Op Amp

Conservative calculation of the required GBW:

M=100 is the gain margin of the Op Amp at a frequency in times;
Fpole is the pole frequency in Hz;
Gfp is the gain at the pole frequency in times.

Christophe Basso in [4] gives another calculation:

M=20 is the gain margin of the Op Amp at a frequency in times;
20 Fcross is the frequency with maximum phase boost in Hz with the factor to account the pole position;
Gfc is the gain at the Fcross frequency in times.

The transfer function of the circuit is:

Add R2 in series with C2. The new transfer function is:

Change the C2 value and find the R2 value:

Now try to use an Op Amp with in this circuit.

Recalculate the circuit values using the equations above and see the result.

Adjust the C2 value:

And finally enter the values into a simulator:

Error compensation for Type 2 compensation network with Op Amp

The top circuit and green color on the charts: the ideal amplifier.
The middle circuit and cyan color on the charts: the Op Amp with GBW of 1 MHz.
The bottom circuit and yellow color on the charts: the Op Amp with GBW of 1 MHz and with the error compensation.

Error compensation for Type II compensation network with Optocoupler without Fast Lane

Type 2 compensation with Optocoupler without Fast Lane

The transfer function of both circuits is (C1=Cz, R1=Rz):

where CTR is the current transfer ratio of the optocoupler.

Add Rc in series with Cp. The new transfer function is:

Change the C2 value and find the Rc value:

Try to use an Op Amp with in this circuit.
Recalculate the circuit values using the equations above and see the result.

Adjust the Cp value:

The extra DC gain is:

And finally enter the values into a simulator:

Error compensation for Type 2 compensation network with Optocoupler without Fast Lane

The top circuit and green color on the charts: the ideal amplifier.
The middle circuit and yellow color on the charts: the Op Amp with GBW of 1 MHz.
The bottom circuit and cyan color on the charts: the Op Amp with GBW of 1 MHz and with the error compensation.
Do not forget that a real optocoupler has a parasitic capacitance and its value should be taken into account.

Conclusion

The described methods help to reduce the requirement to the Gain-Bandwidth of a used Op Amp and cost of circuits.

For filters, they work well with commonly used quality factors below 1.

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Error amp compensation on pwm controller

I’m trying to build a half bridge smps for 325 VDC to 30 VDC using SG3525 controller IC. I have no idea on how to use the error amp on this chip, especially the compensation pin.

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I have seen in some designs the compensation aka «comp» pin which is pin number 9, grounded using a capacitor, in some circuits it is used for negative feedback as in op-amps, in some other design I saw it being directly connected to inverting input, and in some other designs I have seen the comp pin connected to inverting pin with a parallel RC network.

My question is, how to properly use the above mentioned compensation pin in the error amp of SG3525??

1 Answer 1

When in doubt, read the datasheet, apply some circuit design knowledge, and maybe go dig up some applications notes. The SG3525 has become a standard part, so there may even be books written around it.

If you look in the datasheet, you’ll see that the error amplifier gain is stated as a transconductance, with a range of $1.1mathrm . Later on in the datasheet the frequency vs. gain characteristics of the thing are given (Figure 4 in the datasheet that I linked to). The PWM section has thresholds specified (just look at the datasheet).

These three things together, plus your circuit topology and supply voltage, will give you enough information to approximate your power supply as a linear amplifier and calculate its open-loop transfer function; that, in turn, will allow you to calculate the closed-loop transfer function and assess stability. That’ll give you a first cut at the circuit behavior, at which point you’d be wise to do some simulation & testing.

As a first approximation, though, if you hang a capacitor off of the compensation pin, the gain from the error amp inputs to that compensation pin (and, hence, the PWM comparator input) will be $H(s) = frac$ . In other words, the error amp will be a pure integrator. I suspect, given the information in Figure 4, that for all practical purposes the action of the capacitor will swamp out the amplifiers inherent frequency roll-off, and it’ll act like a pure integrator.

As for connecting it back to the inverting input through some feedback resistors or a wire — sure, maybe that’ll work. It’ll turn it into a voltage follower (or voltage amp if there’s more resistance from that pin to ground), which means that there would need to be some compensation outside of the chip to make the loop work.

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Error amplifier compensation desighn in SMPS

MarianB

Member

For some time now the need for SMPS powered from the mains power line has become more and more important so i have decided to give it the proper attention, and i have been documented from many sources, and chosen Marty Brown’s Power supply cookbook as a guide, but the one thing that got me confused is the error amplifier compensation design, and as regulated voltage at the outputs is verry important, the need to understand this topik becomes verry real, i have read the appendix dealing with this but got left with some confusing subjects and i will state them here one by one and i beg you all to bare with me on this since it is verry important to me.

So let’s get down to bussiness, for refference i will name a half bridge forward PSU, with Vin 150V ( on the power transformer primary winding ) and Vout 60V ( the exit to the load voltage ), the power transformer primary winding is of 40 turns and the secondary one is of 32 turns, and i choose an 2 pole 2 zero compensation design, and the first step would be the overall gain of the PSU at DC and a 3 part equation is presented:
[IMGDEAD]http://imageshack.us/a/img843/9598/89110394.png[/IMGDEAD]

My first confusion is right there, to me it seams that every part of the equation gives a different result but still it shouldn’t have, first Adc=Vout/Vin in my example it would be 60/150=0,4; second Adc=(Nsec/Npri)*DC and the result i have obtained is (32/40)*(60/150)=0,32; and last Adc=(Vin/Ve)*(Nsec/Npri), and so with a 3V error amplifier range, it would be (150/3)*(32/40)=50*0,8=40;

This is the first step to take in designing the compensation network so it has to be wright, and so i ask of you to clear my confusion, and let me know why are there different results and wich is the actual gain at DC in my example and the correct way to calculate it.

I may seeam simple to you but it has gave me lots of trouble so i need to clarify it, so thank you all for any cind of response.

More options

MarianB

Member

Seeing as nowone is interested in any cind of answear i helped myself, and reading more thoroughly i found that only the last part of the equation matters in deciding the DC gain, so i started out with the upper example and tested it both graphically and in a simulator ( multisim ), i took in calculation the lowest anticipated Vin witch woulkd be about 86V, the PSU will have a symmetrical output +/-30Vcc, i am monitoring only the possitive rail, and the specs would be:

-Vin(min)=86V
-Vout=30V ( possitive rail monitored )
-Ve=3,5V ( the voltage range of the error amplifier )
-Npri=40 turns
-Nsec=16 turns

The Adc would be:
[IMGDEAD]http://img72.imageshack.us/img72/2645/adc.png[/IMGDEAD]

So Adc=9,82 and Gdc=19,8db.

Now it’s time to draw up the LC characteristic, and i have a inductor of 300uH and 2 paralelled filter caps of 1000u each, and a combined ESR of 33m Ohm, so the LC resonance freq would be 205Hz, and the ESR puts a zero at about 2,4Khz, this is the first graphic:
[IMGDEAD]http://img39.imageshack.us/img39/6055/caracteristicalc.jpg[/IMGDEAD]

Now, next comes the poles and zeroes, and knowing the PSU’s freq is 27Khz i have chosen a crossover freq of 5Khz, and the 2 zeroes at both sides of the Flc, first zero at 40Hz and the second one at 240Hz, the first pole must compensate for the filter caps ESR so it will be at 2,4Khz and the second one needed for stability at high freq, i have chosen it to be at 10Khz, this would be the new graphic with the error amplifier correction drawn in green:
[IMGDEAD]http://img835.imageshack.us/img835/5853/cirectieao3.jpg[/IMGDEAD]

Next step, drawing the global characteristic acoordingly ( the blue line ):
[IMGDEAD]http://img534.imageshack.us/img534/3491/global2d.jpg[/IMGDEAD]

Now the circuit it’s self comes to line up, first the schematic :
[IMGDEAD]http://img213.imageshack.us/img213/471/schemadeprincipiu2p2z.png[/IMGDEAD]

Second the calculation of the components and testing them in the simulator, and for the sake of the correctness of the simulation i’ll imput in multisim the exact values obtained by calculation and if all goes well then i’ll choose standard values, so let’s get on to it:

-The gaind at the first plateau is of 10db, so the Adc=3,16, and i have alreadu chosen R2 at 2k2, so first the obtained Adc must be assured and at the middle of the plateau it is given by R1/R2 so R1=6,95K ( as i sayd i will stick with theese strange vallues for the time beiyng ).
-The first zero at 40Hz is given by R1+C1, so C1=572n.
-The second zero is at 240Hz with R2+C3, so C3=300n.
-The first pole is at 2,4Khz with R3+C3, so R3=220.
-The second pole is at 10Khz with R1+C2, so C2=2,3n.

Now i have all i need to test it in multisim, and this is what i got:
Error amplifier correction-Amplitude
[IMGDEAD]http://img233.imageshack.us/img233/7094/corectiemultisimamplitu.png[/IMGDEAD]

Error amplifier correction-Phase
[IMGDEAD]http://img21.imageshack.us/img21/8782/corectiemultisimfaza.png[/IMGDEAD]

The global obtained-Amplitude
[IMGDEAD]http://img845.imageshack.us/img845/8522/globalmultisimamplitudi.png[/IMGDEAD]

The Global obtained-Phase
[IMGDEAD]http://img819.imageshack.us/img819/543/globalmultisimfaza.png[/IMGDEAD]

And this would be all it seams, and to me it seams to be a good method, granted the poles and zeroes can be choosen differently to give the preffered result, and standard values are needed for the components but the fact is this seams to be a good way to calculate it.

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Соседние файлы в папке PC-POWER

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  06.02.201663.48 Кб22400U.pdf

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  06.02.201649.07 Кб21600PT.pdf

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An error amplifier is most commonly encountered in feedback unidirectional voltage control circuits, where the sampled output voltage of the circuit under control, is fed back and compared to a stable reference voltage. Any difference between the two generates a compensating error voltage which tends to move the output voltage towards the design specification.

An error amplifier is essentially what its name says, that is, it amplifies an error signal. This error is based on the difference between a reference signal and the input signal. It can also be treated as the difference between the two inputs. These are usually used in unison with feedback loops, owing to their self-correcting mechanism. They have an inverting and a non-inverting input pin set, which is what is responsible for the output to be the difference of the inputs.

Devices[edit]

• Discrete Transistors
• Operational amplifiers

Applications[edit]

• Regulated power supply.
• D.C Power Amplifiers
• Measurement Equipment
• Servomechanisms

See also[edit]

• Differential amplifier

External links[edit]

• Error Amplifier Design and Application Archived 28 March 2018 at the Wayback Machine, alphascientific.com. Originally accessed 27 April 2009, now 404. Try https://web.archive.org/web/20081006222215/http://www.alphascientific.com/technotes/technote3.pdf
• Error amplifier as an element in a voltage regulator:
  Stability analysis of low-dropout linear regulators with a PMOS pass element Archived 7 July 2011 at the Wayback Machine

This electronics-related article is a stub. You can help Wikipedia by expanding it.

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Before attempting to compensate a converter, you need to extract the control-to-output transfer function (TF) of the power stage: if a sinusoidal stimulus is applied to the control input of the said converter, how does the signal propagate through the converter to produce an observable response at the output. You have several ways to obtain this TF:

1. Analytical way: derive a small-signal model of the converter and graph its ac response in terms of magnitude and phase. This is a quite lengthy process which requires an equivalent linear circuit from a switching converter. My last book on the subject covers all the necessary steps for completing the process.

2. SPICE simulations: if you have an averaged model of the converter you study, then you can use it to extract the ac response of the power stage by first confirming the operating point is correct.

3. SIMPLIS simulations: SPICE can be used as a frequency-response analyzer (FRA) — see LTspice examples — but it is not very practical in my opinion. SIMPLIS does that natively and you can obtain a Bode plot of the power stage immediately from a switching circuit: no need to resort to an intermediate configuration, just use your cycle-by-cycle model. PSIM also offers this option but in a less easy way I believe.

4. Bench experiments: build a prototype on the bench and extract the response with a FRA.

It is important to understand what contributes poles and zeroes in a converter and going through 1. is important. This is because production, temperature and operating time affect the transfer function and your role, as a designer, is to neutralize its variability. Therefore, seeing where poles and zeroes are located in an equation is important. Then, you can use 2. or 3. to confirm the response and work on a compensation strategy. In the end, 4. will always be the referee, confirming or negating your hypothesis and calculations.

In your case, I will use one of the 60+ SIMPLIS free templates that I posted on my webpage which, for most of them, work with Elements, the free demo. The schematic of a current-mode (CM) push-pull is shown below:

From this circuit, we obtain an operating point (it is crucial to confirm the converter is properly regulating before considering the response — it is true for SIMPLIS but also SPICE of course) and the ac response of the converter:

Now, what is cool, is that I have automated the compensation elements from a macro in which you enter the desired crossover frequency and the phase margin you want. In this example, I have selected a 10-kHz crossover which is already a good value for a fast-responding converter featuring a 60° phase margin:

The components values around the op-amp are then available from the processed netlist.

Ok, so you now see the process — we’ve just scratched the surface here — for compensating a converter. Now, let’s see your points in particular:

1. Do not think of a suitable crossover frequency by solely looking at the switching frequency. Crossover and phase margin selection depends on the transient response you need but also from a given robustness you may need at particular frequencies (i.e. input ripple rejection). Besides, crossover selection is often bounded by the converter itself when you have resonances like in a voltage-mode CCM boost or buck-boost converter for instance or if you have a right-half-plane zero (RHPZ) in the power stage TF. A RHPZ sets a limit for the crossover beyond which you’ll face instabilities. So pulling out of thin air the crossover frequency based on the switching frequency alone is not a correct approach in my opinion. The more you push crossover, the more noise susceptible your converter becomes and you’ll have to deal with issues linked to layout, noise pickup etc. As a preliminary summary, don’t push crossover beyond what is really needed for your performance.

2. No, please go through the process I described as any converter is unique with its own parasitics and components values. With today’s tools, the process is truly eased and you can do a lot on the computer before going to the bench.

3. Please see my answer in 1. and be reasonable with crossover selection.

When all is well stabilized, looking at the transient response is one way to check the converter adequately reacts when subjected to a load step: