Error hdlcompiler 806

I am new to Verilog and I'm keep getting these compile errors. I've googled the error, but i didn't get an answer. Here is my code and the errors. always @(*) begin //seed=32'habcd123cd;//ass...

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I am new to Verilog and I’m keep getting these compile errors. I’ve googled the error, but i didn’t get an answer. Here is my code and the errors.

always @(*) begin
     //seed=32'habcd123cd;//assigning seed
     if(posedge axi_clk & first[0]) begin
          load_seed=1'b1;
     end

     if(load_seed) begin
          first[1]=1'b1;
     end

     if(negedge axi_clk & first[1]) begin
          load_seed=1'b0;
          first=2'b00;
     end
 end

My errors

ERROR:HDLCompiler:806 — «K:/final project/codes/v2/input_arbiter.v» Line 252: Syntax error near «posedge».
ERROR:HDLCompiler:806 — «K:/final project/codes/v2/input_arbiter.v» Line 258: Syntax error near «negedge».
ERROR:HDLCompiler:598 — «K:/final project/codes/v2/input_arbiter.v» Line 46: Module ignored due to previous errors.

Qiu's user avatar

Qiu

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asked Aug 18, 2015 at 9:14

MRNakh's user avatar

You’re using posedge/negedge in a wrong way. These keywords should be used in a sensitivity list of always block, e.g.:

always @(posedge clk)

or 

always @(negedge clk)

always @(*) is used to describe combinational logic, or logic gates. What you’re trying to achieve is sequential logic.

You should also know (please refer to this topic) that

when you assign to a register in an edge-sensitive always block, you’re defining a flip-flop. FPGAs do not have flip-flops that can trigger on both edges of a clock. That’s why you need two separate always blocks, one for each edge of the clock, and then figure out a way to combine the outputs of the two blocks without creating glitches.

Community's user avatar

answered Aug 18, 2015 at 10:11

Qiu's user avatar

QiuQiu

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Источник

I keep getting errors below in ISE, and can not figure out the real problems. anyone has any clues?

error messages:

ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 29: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 39: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 43: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 47: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 50: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 54: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 64: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 68: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 72: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 75: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 88: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 98: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 102: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 106: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 109: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 113: Syntax error near "posedge".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 123: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 127: Syntax error near "<=".
ERROR:HDLCompiler:806 - "C:UsersRayDocumentsprojectQFCQFC_A.v" Line 131: Syntax error near "<=".

and here is my code:

`timescale 1ns/1ps

module QFC_A #
(
    parameter SPI_CYCLE   = 100000,
    parameter MASTER_ID   = 8'h66,
    parameter SLAVE_ID    = 8'h66
)

(
    input i_axi_lite_s_aclk,
    input i_rst,
    input i_din,
    output o_en,
    output o_dout
);



reg [255:0] r_frame_message;
reg [3:0] r_cnt_message;
wire [31:0] w_frame_word_message;
wire w_message_rd_en;
wire w_id_match_message;
wire w_message_empty;
wire w_message_ready;


always @ (posedge i_axi_lite_s_aclk & posedge i_rst)
    begin
        if (i_rst)
            begin
                r_frame_message <= 256'h0;
            end
        else
            begin
                if (w_id_match_message & (r_cnt_message != 4'hf))
                    begin
                    r_frame_message <= {224'h0, w_frame_word_message};
                    end
                else if (w_message_rd_en & w_message_empty)
                    begin
                        r_frame_message <= 256'h0;
                    end
                else if (w_message_rd_en)
                    begin
                        r_frame_message <= {r_frame_message[223:0], w_frame_word_message};
                    end
            end
    end

assign w_id_match_message = (w_frame_word_message[23:16] == MASTER_ID)? 1'b1 : 1'b0;

always @ (posedge i_axi_lite_s_aclk & posedge i_rst)
    begin
        if (i_rst)
            begin
                r_cnt_message <= 4'h0;
            end
        else if (w_message_rd_en)
            begin
                if (w_id_match_message)
                    begin
                        r_cnt_message <= 4'h0;
                    end
                else if (r_cnt_message == 4'hf)
                    begin
                        r_cnt_message <= 4'h0;
                    end
                else
                    begin
                        r_cnt_message <= r_cnt_message + 4'h1;
                    end
            end
    end

assign w_message_ready = (r_cnt_message == 4'hf & ~w_send_ready)? 1'b1 : 1'b0;  

reg [255:0] r_frame_data;
reg [3:0] r_cnt_data;
wire [31:0] w_frame_word_data;
wire w_data_rd_en;
wire w_id_match_data;
wire w_data_empty;
wire w_data_ready;


always @ (posedge i_axi_lite_s_aclk & posedge i_rst)
    begin
        if (i_rst)
            begin
                r_frame_data <= 256'h0;
            end
        else
            begin
                if (w_id_match_data & (r_cnt_data != 4'hf))
                    begin
                        r_frame_data <= {224'h0, w_frame_word_data};
                    end
                else if (w_data_rd_en & w_data_empty)
                    begin
                        r_frame_data <= 256'h0;
                    end
                else if (w_data_rd_en)
                    begin
                        r_frame_data <= {r_frame_data[223:0], w_frame_word_data};
                    end
            end
    end

assign w_id_match_data = (w_frame_word_data[23:16] == MASTER_ID)? 1'b1 : 1'b0;

always @ (posedge i_axi_lite_s_aclk & posedge i_rst)
    begin
        if (i_rst)
            begin
                r_cnt_data <= 4'h0;
            end
        else if (w_data_rd_en)
            begin
                if (w_id_match_data)
                    begin
                        r_cnt_data <= 4'h0;
                    end
                else if (r_cnt_data == 4'hf)
                    begin
                        r_cnt_data <= 4'h0;
                    end
                else
                    begin
                        r_cnt_data <= r_cnt_data + 4'h1;
                    end
            end
    end

assign w_data_ready = (r_cnt_data == 4'hf & ~w_send_ready)? 1'b1 : 1'b0;    

reg [255:0] r_frame_rec;
reg [3:0] r_cnt_rec;
wire[31:0] w_frame_word_rec;
wire w_rec_en;
wire w_id_match_rec;
wire w_rec_ready;
wire w_rec_success;

always @ (posedge i_axi_lite_s_aclk & posedge i_rst)
    begin
        if (i_rst)
            begin
                r_frame_rec <= 256'h0;
            end
        else
            begin
                if (w_id_match_rec & (r_cnt_rec != 4'hf))
                    begin
                        r_frame_rec <= {224'h0, w_frame_word_rec};
                    end
                else if (w_rec_en)
                    begin
                        r_frame_rec <= {r_frame_rec[223:0], w_frame_word_rec};
                    end
            end
    end

assign w_id_match_rec = (w_frame_word_rec[23:16] == SLAVE_ID)? 1'b1 : 1'b0;

always @ (posedge i_axi_lite_s_aclk & posedge i_rst)
    begin
        if (i_rst)
            begin
                r_cnt_rec <= 4'h0;
            end
        else if (w_rec_en)
            begin
                if (w_id_match_rec)
                    begin
                        r_cnt_rec <= 4'h0;
                    end
                else if (r_cnt_rec == 4'hf)
                    begin
                        r_cnt_rec <= 4'h0;
                    end
                else
                    begin
                        r_cnt_rec <= r_cnt_rec + 4'h1;
                    end
            end
    end

assign w_rec_ready = (r_cnt_rec == 4'hf)? 1'b1 : 1'b0;      
assign w_rec_success = ((w_rec_ready) & (r_frame_rec[251] == 1'b1) & (checksum(r_frame_rec[239:16]) == r_frame_rec[15:0]))? 1'b1 : 1'b0;    

reg [2:0] r_current_state;
reg [2:0] r_next_state;
reg [16:0] r_cycle_timer;
reg [14:0] r_trans_timer;
reg [1:0] r_cycle_s;
reg [223:0] r_payload;
reg [255:0] r_frame_send;
wire w_cycle;
wire w_cycle_pos;
wire w_state_start;
localparam IDLE          = 3'h0;
localparam SEND_MSG      = 3'h1;
localparam RESEND_MSG    = 3'h2;
localparam SEND_DATA     = 3'h3;
localparam RCG_ACK       = 3'h4;
localparam CHANGE_TLG    = 3'h5;
localparam ABORT_MSG     = 3'h6;

always @ (posedge i_axi_lite_s_aclk & posedge i_rst)
    begin
        if (i_rst)
            begin
                r_cycle_timer <= 16'h0;
            end
        else if (r_cycle_timer < SPI_CYCLE)
            begin
                r_cycle_timer <= r_cycle_timer + 16'h1;
            end
        else
            begin
                r_cycle_timer <= 16'h0;
            end
    end

assign w_cycle = (r_cycle_timer == SPI_CYCLE)? 1'b1 : 1'b0;

always @ (posedge i_axi_lite_s_aclk & posedge i_rst)
    begin
        if(i_rst)
            begin
                r_cycle_s <= 2'h0;
            end
        else
            begin
                r_cycle_s <= {r_cycle_s[0], w_cycle};
            end
    end

assign w_cycle_pos = (~r_cycle_s[1] & r_cycle_s[0]);


function reg [15:0] checksum (input reg [223:0] r_frame)
    begin
        integer i;
        reg [15:0] r_sum_1;
        reg [15:0] r_sum_2;

        r_sum_1 = 16'hff;
        r_sum_2 = 16'hff;
        for (i = 0; i < 28; i++)
            begin
                r_sum_1 = r_sum_1 + r_frame[(223-8*i)-:8];
                r_sum_2 = r_sum_1 + r_sum_2;
                if (i == 20)
                    begin
                        r_sum_1 = ( r_sum_1 >> 8 ) + ( r_sum_1 & 8'hff);
                        r_sum_2 = ( r_sum_2 >> 8 ) + ( r_sum_2 & 8'hff);
                    end
            end
        r_sum_1 = ( r_sum_1 >> 8 ) + ( r_sum_1 & 8'hff);
        r_sum_2 = ( r_sum_2 >> 8 ) + ( r_sum_2 & 8'hff);
        r_sum_1 = ( r_sum_1 >> 8 ) + ( r_sum_1 & 8'hff);
        r_sum_2 = ( r_sum_2 >> 8 ) + ( r_sum_2 & 8'hff);
        checksum = (r_sum_1 << 8) | r_sum_2;
    end
endfunction



always @ (*)
    begin
        case (r_current_state)
            IDLE:               begin
                                    r_next_state = SEND_DATA;
                                    r_frame_send = {8'h90, MASTER_ID, 240'h0};
                                end
            SEND_MSG:           begin
                                    r_next_state = RCG_ACK;
                                    if (w_state_start)
                                        begin
                                            w_message_rd_en = 1'b1;
                                            w_send_ready = 1'b0;
                                            w_state_start = 1'b0;
                                        end
                                    if (r_frame_message == 256'h0)
                                        begin
                                            w_message_rd_en = 1'b0;
                                            r_frame_send = {r_frame_send[], MASTER_ID, 240'h0};
                                        end
                                    else if
                                end
            RCG_ACK:            begin
                                    if (w_rec_success)
                                        begin
                                            r_next_state = CHANGE_TLG;
                                        end
                                    else if (r_resend_cnt == 2'b11)
                                            begin
                                                r_next_state = ABORT_MSG;
                                            end
                                end
        endcase
    end

endmodule

Источник

$begingroup$

I am trying to implement one of the ciphers in VHDL.

I have 2 entities: Main and block_cipher

The Main entity also have a parameter named mode which is of type : std_logic

So from main entity I want to call block_cipher on the basis of the mode value.

e.g.

blk_cipher_prc : process(mode)
begin
 if(mode = 0) then
    block_cipher_0 : block_cipher port map (text, key,output);
 end if;
end process;

But it gives me an error: ERROR:HDLCompiler:806 Syntax error near «port».

My only motive is to call the other entity on the basis of the mode value, If someone can help with my code or can provide some alternative way to do it.

asked Jul 1, 2016 at 20:52

TechJ's user avatar

$endgroup$

4

$begingroup$

Forgive any wrong interpretations but your terminology (code, call) suggests you may see VHDL as a ‘program’. It is instead a descriptor language for describing a digital electronic circuit. Recognising that distinction is paramount and you’ll get confused if you don’t see it clearly and unambiguously. Try to see VHDL as what it is at its heart: a glorified circuit diagram. Avoid mental comparisons with software and computer programs, which are very different.

Describing VHDL further for what you need is beyond this post. But your source file should instantiate (‘connect up the wires of’) your component outside of any process within your architecture.

answered Jul 2, 2016 at 20:11

TonyM's user avatar

TonyMTonyM

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the error is near the <clock>

can someone help me :D

ARCHITECTURE behavior OF eight_by_four_sram_test_bench IS

-- Component Declaration for the Unit Under Test (UUT)


COMPONENT eight_by_four_sram


PORT(
	
     address : IN  std_logic_vector(2 downto 0);

     read_notwrite : IN  std_logic;

     chip_select : IN  std_logic;

     data_inout : INOUT  std_logic_vector(3 downto 0)

    );

END COMPONENT;

—Inputs

signal address : std_logic_vector(2 downto 0) := (others => ‘0’);

signal read_notwrite : std_logic := ‘0’;

signal chip_select : std_logic := ‘0’;

--BiDirs

signal data_inout : std_logic_vector(3 downto 0);

— No clocks detected in port list. Replace <clock> below with

— appropriate port name

constant <clock> period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: eight_by_four_sram PORT MAP (

      address => address,

      read_notwrite => read_notwrite,

      chip_select => chip_select,

      data_inout => data_inout

    );

— Clock process definitions

<clock> process :process

begin <clock> <= ‘0’;

	wait for <clock> period/2;

	<clock> <= '1';

	wait for <clock> period/2;

end process;

— Stimulus process

stim_proc: process begin

  -- hold reset state for 100 ns.

  wait for 100 ns;	

  wait for <clock> period*10;

  -- insert stimulus here 

  wait;

end process;

END;

HDLCompiler:806 Syntax error near «<«.

Источник

Строка 51 с орфографической ошибкой process по линии 50 (разрушится следующие ошибки на линиях 54, 58)

Строка 63 Roll='1' должна быть Roll <= '1' (Будут свернуть строки ошибок 64, 65).

Строка 69: else Sp ='1'; Nextstate <= 4; else Sp ='1'; Nextstate <= 4; должно быть else Sp <= '1'; Nextstate <= 4; else Sp <= '1'; Nextstate <= 4;

Строка 68: (не указана как ошибка), else if должно быть elsif

Строка 88: (не указана как ошибка), then Roll = '1'; должен быть then Roll <= '1';

Затем это анализирует и уточняет (и мы не утверждаем, что это правильно, стремление переформатировать отступы и пробелы почти подавляющее).

(И это говорит нам, что вы должны использовать согласованное отступы и белое пространство, чтобы они выделялись).

Также обратите внимание, что единственное условие использования, которое необходимо,

use IEEE.STD_LOGIC_1164.ALL;

Остальные из них используют условия — шум.

(И здесь, надеясь, что подсчет моих пальцев и пальцев ног получил исходные номера строк прямо из ваших сообщений об ошибках и несоответствие образцов VHDL).

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VHDL errors in my code?


  • Thread starter

    Jorge Jesse Cantu


  • Start date

    Apr 27, 2014

Status
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  • #1

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Hi guys! I just coded a 4 to 2 priority encoder and am getting the following errors:

ERROR:HDLCompiler:806 — «C:UsersOwnerDocumentsvhdlencoderpriorityencoder.vhd» Line 47: Syntax error near «process».
ERROR:HDLCompiler:841 — «C:UsersOwnerDocumentsvhdlencoderpriorityencoder.vhd» Line 48: Expecting type void for <behavioral>.

How do I fix these? Here is my code:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity priorityencoder is
    port(en_l: in std_logic;                            --Active low enable
          din: in std_logic_vector(3 downto 0); --Active high data input
          dv_l: out std_logic;                          --Valid output active low
          dout: out std_logic_vector(1 downto 0)  --Active high data output
          );
          
end priorityencoder;
 
architecture Behavioral of priorityencoder is
signal en: std_logic;
signal dv: std_logic;
 
begin
en <= not en_l;     --Activation level conversion
dv_l <= not dv;     --Activation level conversion
 
process(din, en)
begin
    if(en = '1' and dv = '1') then
        if(din(0) = '1') then
            dout <= "11";           --LSB has priority
        if(din(1) = '1') then
            dout <= "10";
        if(din(2) = '1') then
            dout <= "01";
        if(din(3) = '1') then   --MSB has least priority
            dout <= "00";
        end if;
    elsif(en = '0') then
        dv <= '0';
        dout <= "00";       
    end if; 
end process;
end Behavioral;

Last edited: Apr 27, 2014

  • #2

Hi guys! I just coded a 4 to 2 priority encoder and am getting the following errors:

How do I fix these? Here is my code:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity priorityencoder is
    port(en_l: in std_logic;                            --Active low enable
          din: in std_logic_vector(3 downto 0); --Active high data input
          dv_l: out std_logic;                          --Valid output active low
          dout: out std_logic_vector(1 downto 0)  --Active high data output
          );
          
end priorityencoder;
 
architecture Behavioral of priorityencoder is
signal en: std_logic;
signal dv: std_logic;
 
begin
en <= not en_l;     --Activation level conversion
dv_l <= not dv;     --Activation level conversion
 
process(din, en)
begin
    if(en = '1' and dv = '1') then
        if(din(0) = '1') then
            dout <= "11";           --LSB has priority
        if(din(1) = '1') then
            dout <= "10";
        if(din(2) = '1') then
            dout <= "01";
        if(din(3) = '1') then   --MSB has least priority
            dout <= "00";
        end if;
    else
        en <= '0';
        dv <= '0';
        dout <= "00";
    end if; 
end process;
end Behavioral;

Your if statement is incorrect and should have the following structure when nested.

Code VHDL - [expand]
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if  <comparison> then
elsif <comparison> then
elsif <comparison> then
end if;

  • #3

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Thanks I edited my code above. But I am still getting this error:

ERROR:HDLCompiler:806 - "C:/Users/Owner/Documents/vhdl/encoder/priorityencoder.vhd" Line 46: Syntax error near "process".

  • #4

You’re compiling some other code because I don’t see any line 46 in the code you posted, and I don’t get any compilation error.

— — — Updated — — —

You’ve also got problems with assigning en <= not en_l; and then later in the process assigning it with en <= ‘0’;, which results in multiple drivers. These don’t result in compilation errors in Vivado xsim but they are incorrect.

You also have issues with how the dv signal is driven.

Basically this code shows that you need to read up on how to code proper VHDL, what you’ve got now is a mess, which synthesizes to a inputs for en_l and din but they aren’t connected to the outputs at all.

Regards

— — — Updated — — —

Maybe you should look at this site, which shows you how you should code a priority encoder.

https://www.asic-world.com/examples/vhdl/pri_encoder.html

Last edited: Apr 28, 2014

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  • Digital Design and Embedded Programming

  • PLD, SPLD, GAL, CPLD, FPGA Design

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Доброго дня всем. Такой вопрос. Вылетает ошибка «ERROR:HDLCompiler:806-Line 33: Syntax error near «entity».»
Синтаксис написан верно (вроде). Смысловая составляющая тоже вроде есть. Подскажите, что мне делать пожалуйста.
P.s. еще очень замучала ошибка «design is empty». Если кто знает, что с ней делать, тоже была бы неплоха информация.
Спасибо.

entity massive is
    port ( 
            clk     : in std_logic;
            reset : in std_logic;
            sin     : out std_logic_vector(15 downto 0));
end massive;

architecture Behavioral of massive is
    type my_type is array (0 to 16) of signed (14 downto 0);
    signal x : my_type;
    signal y : my_type;
    signal z : my_type;
    signal j : my_type := ("001111111001000", "001101111100010", "001101101101010", "000110111101010", "000011011111100", 
                                                                    "000001101111110", "000000110111111", "000000011100000", "000000001110000", "000000000111000",
                                                                     "000000000011100", "000000000001110", "000000000000110", "000000000000011", "000000001000010",
                                                                     "000000000000010", "000000000000001");
    signal x1 : std_logic_vector(15 downto 0);
    signal y1 : std_logic_vector(15 downto 0);
    signal z1 : std_logic_vector(15 downto 0);

begin
process(clk, reset)                                                                   
begin
        if rising_edge(clk) then
            if reset <= '1' then
                for i in 0 to 15 loop
                    if (z(i) >= '0') then 
                        x1(i) <= x(i+1) - (y(i+1)/2**i);
                        y1(i) <= y(i+1) + (x(i+1)/2**i);
                        z1(i) <= z(i) - j(i);
                    else
                        x1(i) <= x(i+1) + (y(i+1)/2**i);
                        y1(i) <= y(i+1) - (x(i+1)/2**i);
                        z1(i) <= z(i) + j(i);
                    end if;
                sin <= y1;
                end loop;
            end if;
        end if;
end process;
end Behavioral;

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