Error internal time step too small in transient analysis - Исправление ошибок и поиск оптимальных решений проблем

Convergence defined

To do its work, Micro-Cap 9 must solve nonlinear equations. Neither people nor

computers are able to solve these equations analytically, so they must be solved

numerically. There are many techniques for numerically solving equations, but

they all rely upon a rule that tells the algorithm when to stop. Usually it is embodied

in a piece of code like this:

while (error > RELTOL*V + VNTOL and iterations < MAXITERATIONS)

{

error=Solve();

iterations = iterations +1;

}

This code says to continue iterating the solution while the error is greater than

some tolerance and we have not yet exceeded the specified maximum number of

iterations. The error itself is defined as the difference in successive estimates of

the final answer. Thus, if we get the same answer from one iteration to the next,

or at least the difference between two successive answers is less than some acceptable

tolerance then we say the solution converged, and the answer at this one

data point is deemed correct.

This criteria is checked for every nonlinear variable in the circuit. If any one of

these variables fails to converge, then the infamous message,

«Internal time step too small»,

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How to fix «timestep too small» error in hspice si

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Hughes
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Jun 10, 2003

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Hughes

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internal timestep too small in transient analysis

Anyone know which options will help to solve this problem?

Guest

timestep too small

What exactly are you doing? What does your forcefile look like?

kfy

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internal timestep too small

Anyone know which options will help to solve this problem?

relv=2 …
or change the voltage or temperature in minor

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hspice internal timestep too small

If i am not mistaken, what it means is the timestep specified in the spice simulation file is too small.

Example (for transient analysis):

.tran 0.01ns 360ns

The «0.01ns» is your timestep to run the transient analysis till 360ns. Perhaps you should increase it to 0.1ns.

Hughes

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spice timestep too small

Thanks all.
My problem should be «internal timestep too small».
Transient analysis timestep has little effect to this problem.
Simetimes I made a small change to the circuit and the problem dispeared. But when circuits arelarge, it is hard to find a solution by this way. So I want to know which spice options will help to solve this problem.

I will try kfy’s solution next time I encounter this problem. Thank you.

lll

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time step too small

I also meet this problem in orcad (pspice).
After increase the default convergence times (maybe K4 in orcad9) from 10 too 200, many Transient analysis can run but the speed is slow.

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timestep too small spice

«timestep too small»— Transient Convergence Problem:

Solution:
0. Check circuit topology and connectivity.
This item is the same as item 0 in the DC analysis.

1. Set RELTOL=.01 in the .OPTIONS statement.
Example: .OPTIONS RELTOL=.01

2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
Example: . OPTION ABSTOL=1N VNTOL=1M

3. Set ITL4=500 in the .OPTIONS statement.
Example: .OPTIONS ITL4=500

4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.

5. Reduce the rise/fall times of the PULSE sources.
Example: VCC 1 0 PULSE 0 1 0 0 0
becomes VCC 1 0 PULSE 0 1 0 1U 1U

6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
Example: .OPTIONS RAMPTIME=10NS

7. Add UIC (Use Initial Conditions) to the .TRAN line.
Example: .TRAN .1N 100N UIC

8. Change the integration method to Gear (See also Special Cases below).
Example: .OPTIONS METHOD=GEAR

Regards,

srik

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tran timestep too small

to solve convergence problems

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hspice timestep too small

Internal timestamp too small is usually due to the fact that hspice cannot find the derivative of a waveform. (Usuallly means that the derivative is inifinity) Hspice calculates (I think) the running derivative of the signal and adjusts the timestep accordingly. If it cannot find the derivative, it barfs. I have found that taking the time to check the initialization of all nodes usually helps.

Just a thought,

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altium timestep too small

If i am not mistaken, what it means is the timestep specified in the spice simulation file is too small.

Example (for transient analysis):

.tran 0.01ns 360ns

*the «0.01ns» is not your timestep to run the transient analysis, it is print step
The «0.01ns» is your timestep to run the transient analysis till 360ns. Perhaps you should increase it to 0.1ns.

Hughes

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spice time step too small

Hi, rambus_ddr. I don’t know what you mean by quoting crystal’s input. But internal timestep is definitely not the same as the step in transient analysis statement. The latter is just a step for output. I think rambus_ddr and srik’s solution is very helpful.

okguy

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hspice internal timestep too small#

ITL4 is limited to 100 now in the new versions of HSPICE.

OkGuy

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timestamp too small

The timestep used by HPSPICE when making a transient simulation is changed dynamically, i.e., HSPICE always tries to find the maximum timestep that still guarantees a given precision. Several different algorithms can be selected to determine the timestep to use — for details refer to HSPICE manual.

The timestep specified in the .tran line (TSTEP) serves two main purposes:
1. Print step (used by .print statements)
2. Helps to define that MAXIMUM and MINIMUM internal timestep used in the simulation.

The «internal timestep too small» error happens when HSPICE tries to use an internal timestep bellow a certain threshold. This threshold is given by:
MIN TIMESTEP=TSTEP*RMIN
where RMIN is an option that can be set by the user (default=1e-9).

For example if one specifies
.tran 0.01ns 360ns

we have TSTEP=0.01ns and the default internal timestep is 0.01ns*1e-9=1e-20 s

So, one solution to the problem is to specify a smaller RMIN (I think that the minimum value is 1e-15…). This solved the problem most of the times I faced it.

If you still have this problem you can try to play with the others parameters that control the internal timestep (see the manual).

Regards

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«timestep too small»— Transient Convergence Problem:

I have done all of the above advices, but it did not work.
Now, I try to use «.options accurate=1 gmin=1e-9» and it’s work well.

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Two main things.

One, every active device must have realistic capacitances between
all nodes. Too low a capacitance lets voltage swing crazy with a
tiny charge error.

Two, every device must be well behaved at abnormal terminal
bias conditions. There can be no singularities (BSIMSOI is very
bad about this) anywhere and no blowups when you take a
pin voltage well outside normal range. Modeling dudes don’t
have data for that and don’t check it. But by 1kV pin-pin
or 1kA forced current you had better still look like a
finte valued resistor. When 1kV gets you 1MA by some
bullschnitzel square law approximation you are in trouble
anytime the numerical algorithm steps off into the weeds.
You need the device to be solvable over a much, much
wider range than you will ever use it.

If tweaking settings doesn’t work that’s a pretty good
sign that it isn’t a settings problem. Sacrificing accuracy
to get convergence means your model is numerically
bad (accuracy aside). And some models depend on the
alignment of a lot of parameters to «cover up» some
fundamental singularities (like where region of operation
and equations transition). When you get to Monte Carlo
and start random-messing parameters around you can
expose «unexplored territory».

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hiii shiowjyh

can u plz tell some more information regarding transient convergence problems?? how to overcome those??

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Hello all,

«time step specified too small»

I have been getting this error even when I tried all your above mentioned comments.
The interesting point about my circuit is I didn’t mention any timestep or timestop for my transient analysis.
I am doing optimization and so I wrote the command based on the information in this link:

**broken link removed**

So my netlist includes this line:

.Tran Data=frq Sweep optimize=opt1 results=comp1 model=optmodel

What do you think?

Thanks in advance
Analogstudent

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If you tried replicating the schematic from the datasheet at page 14, you didn’t do a good job: you missed the output feedback network. And you chose a 1k value for the output load, which is questionable for an output that’s meant to deliver 3.3 V @ 3 A; I’ve made it 1 Ω. Not lastly, C1 and C2 are useless without some series resistance between the supply and them.

That said, the model works, though, for some reason, the output doesn’t stabilize at 3.3 V. The soft-start is meant to bring up the output after some 500 µs; the duration is right, the value is not. To be sure we’re talking about the same thing, this is the model I used. The symbol is auto-generated so you won’t have problems replicating my schematic.

Still, I’ve made the following modifications (seen in the picture, below), though you may get lucky and not need any:

added Rser=1m to the bootstrap capacitor
added Rser=50m to the output filter capacitor
added Rser=10m Cpar=1m to the input voltage source
added uic to the simulation card since LTspice has trouble finding an operating point; just start from zero and it will be fine.

works

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