Error invalid module instantiation

Ошибка «Invalid Module Instantiation» в детекторе последовательности Мили — Verilog Я определил модуль для конечного автомата Мили, который обнаруживает определенную последовательность. Я не кодировал состояния, поскольку обычно это лучший выбор, поскольку я хотел сделать это по-другому (я видел аналогичный пример в книге, но код был на VHDL). При компиляции кода я получаю следующие ошибки. […]

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  1. Ошибка «Invalid Module Instantiation» в детекторе последовательности Мили — Verilog
  2. Verilog Translator
  3. Ошибка «Invalid Module Instantiation» Ошибка в детекторе последовательности Мили — Verilog
  4. Icarus Verilog Bugs
  5. Group
  6. Searches
  7. #492 Mixed port module instantiation says just «syntax error»
  8. Discussion
  9. Ошибка «Invalid Module Instantiation» в детекторе последовательности Мили — Verilog
  10. 3 ответа

Ошибка «Invalid Module Instantiation» в детекторе последовательности Мили — Verilog

Я определил модуль для конечного автомата Мили, который обнаруживает определенную последовательность. Я не кодировал состояния, поскольку обычно это лучший выбор, поскольку я хотел сделать это по-другому (я видел аналогичный пример в книге, но код был на VHDL).

При компиляции кода я получаю следующие ошибки.

Я ничего не могу разобрать из сообщения об ошибке. Может кто-нибудь объяснить сообщение об ошибке и предложить, как ее исправить?

В вашем всегда блоке отсутствуют ключевые слова начала и конца. Код думает, что вы пытаетесь создать экземпляр модуля, а не назначать сигналы. Только первая строка будет захвачена в блоке always (назначение Q1). Остальные — нет. Попробуй это:

Кстати, этот код действительно ужасен. Есть лучший способ сделать это??

У вас несколько синтаксических ошибок.

Вам нужен begin/end в вашем always блоке.

Даже после исправления этого в вашем коде будут стоять беспорядочные точки с запятой:

По совпадению, это текущее задание в моем классе продвинутой логики CPE166. Основная идея в задании — правильно синтезировать регистры. Что-то вроде этого (хотя наше назначение было намного сложнее с несколькими возможными входами, более длинными последовательностями, сбросом, программируемыми последовательностями и кнопками, которые необходимо было заблокировать):

Это создаст 4-битный регистр сдвига, который будет сдвигаться по каждому положительному фронту тактового сигнала. Самое новое значение x_in войдет в одну сторону, а самое старое значение x_in будет сдвинуто. Текущие значения сдвигового регистра постоянно сравниваются с параметром correct_sequence , который, когда истинно, приведет к увеличению y_out.

Источник

Verilog Translator

The bugs are listed here can be reproduced on tests for Verilog Translator project (so called «ieee-tests»).

Cause: attributes for «case» statement branches like «(* full_case, parallel_case *)» are unsupported.
test_03_08_01_2.v

Cause: attributes for «case» statement branches like «(* full_case *)» are unsupported.
test_03_08_01_6.v

Cause: attributes for assignments like «a = b + (* mode = «cla» *) c;» are unsupported.
test_03_08_01_7.v

Cause: attributes for assignments like «a = add (* mode = «cla» *) (b, c);» are unsupported.
test_03_08_01_8.v

Cause: attributes for assignments like «a = b ? (* no_glitch *) c : d;» are unsupported.
test_04_03_01_1.v

Cause: cannot parse «trireg (small) storeit;»
test_04_03_02_1.v

Cause: cannot parse «tri1 scalared [63:0] bus64;»
test_04_04_01_1.v

Cause: cannot parse «trireg a;»
test_04_09_03_1_1.v

Cause: cannot parse «reg arrayb[7:0][0:255];»
test_04_09_03_1_2.v

Cause: cannot parse «reg arrayb[7:0][0:255];»
test_04_10_03_2.v

Cause: the «specparam» is unsupported.
test_05_01_14_1.v

Cause: cannot parse «result = ;»
test_05_02_01_4.v

Cause: cannot parse «addr = x;»
test_05_02_02_2.v

Cause: cnnot parse «wire threed_array[0:255][0:255][0:7];»
test_05_03_00_1.v

Cause: «parameter val = (32’d 50: 32’d 75: 32’d 100);»
test_06_01_03_1.v

Cause: «wire #10 wireA;»
test_07_14_01_1.v

Cause: «bufif0 #(5:7:9, 8:10:12, 15:18:21) b1 (io1, io2, dir);»
test_07_14_01_2.v

Cause: » #(95:100:105) clk = 1;»
test_07_14_02_2_1.v

Cause: «trireg ( large ) #(0,0,50) cap1;»
test_07_14_02_2_2.v

Cause: «trireg ( large ) #(0,0,50) cap1;»

  • test_08_06_00_1.v
  • test_08_07_00_1.v

    Cause: » ? ?? 01 : ? : 1 ;»
    test_09_06_00_1.v

    Cause: «begin : mult»
    test_09_06_00_2.v

    Cause: «begin : count1s»
    test_09_07_05_4.v

    Cause: » * // equivalent to (c or d)
    x = c ^ d;»
    test_09_07_07_1.v

    Cause: «repeat (-3) @ (posedge clk)»
    test_10_03_00_5.v

    Cause: «begin : posedge(clk)»
    test_12_02_00_1.v

    Cause: «else;»
    test_14_03_00_1.v

    Cause:

    test_17_02_04_4_1.v

    Источник

    Ошибка «Invalid Module Instantiation» Ошибка в детекторе последовательности Мили — Verilog

    Я определил модуль для машины состояния Мили, которая обнаруживает определенную последовательность. Я не кодировал состояния, как правило, лучший выбор, поскольку я хотел сделать это по-другому (я видел аналогичный пример в книге, но код был в VHDL).

    При компиляции кода я получаю следующие ошибки.

    Я ничего не могу понять из сообщения об ошибке. Может кто-нибудь объяснить сообщение об ошибке и предложить, как его исправить?

    Вам не хватает начального и конечного ключевых слов в вашем блоке всегда. В коде предполагается, что вы пытаетесь создать экземпляр модуля, а не назначать сигналы. Только первая строка будет записана под всегда блоком (назначение Q1). Остальные не будут. Попробуй это:

    Как примечание, этот код действительно действительно уродлив. Есть лучший способ сделать это??

    Кстати, это текущее задание в моем классе усовершенствованного логического проектирования CPE166. Основная идея в задании — правильно синтезировать регистры. Что-то вроде этого (хотя наше назначение было намного сложнее с несколькими возможными входами, более длинными последовательностями, сбросом, программируемыми последовательностями и кнопками, которые нужно было отбросить):

    Это создаст 4-битный регистр сдвига, который сдвинется на каждый положительный фронт тактового сигнала. Новейшее значение x_in будет идти с одной стороны, и самое старое значение x_in будет сдвинуто. Текущие значения сдвигового регистра постоянно сравниваются с параметром correct_sequence , который, когда true сделает y_out, будет высоким.

    Источник

    Icarus Verilog Bugs

    Group

    Searches

    #492 Mixed port module instantiation says just «syntax error»

    I had this line of code:

    phaser ph(.clock_1x(clock), .clock_2x(clock_2x), reset_, phase);

    The problem is that reset_ and phase are not passed by name while the clocks are. It took me a while to figure that out because the error message is very uninformative:

    xp10/xp10_bridge_wrapper.v:384: syntax error
    xp10/xp10_bridge_wrapper.v:384: error: Invalid module instantiation

    Could you make that a bit more elaborate?

    Discussion

    Logged In: YES
    user_id=1651735
    Originator: NO

    While I’m sure we can build a test case for this, just showing a single line is a bit limited. How are the signals defined at the top level and in the module? Attaching a real working example would be most helpful! I’m assuming this is for the development branch so I’m setting that and the category as well.

    • labels: —> Verilog compiler bug
    • milestone: —> devel

    Logged In: YES
    user_id=606738
    Originator: YES

    See the code below. Like I say, this is a bug in the code, so it’s correct for Icarus to quit on error. I had just wished that the message was more informative. On reflection, it IS just a syntax error, so don’t make this alone a high priority so much as generally trying to make Icarus error messages more informative. Of course, it’s already more informative than some simulators I’ve used in the past! But I want Icarus to take over the world, you see. 🙂

    wire clock, clock_2x, reset_, phase;

    phaser ph(.clock_1x(clock), .clock_2x(clock_2x), reset_, phase);

    module phaser(clock_1x, clock_2x, reset_, phase);

    input clock_1x, clock_2x, reset_;
    output phase;

    Источник

    Ошибка «Invalid Module Instantiation» в детекторе последовательности Мили — Verilog

    Я определил модуль для конечного автомата Мили, который обнаруживает определенную последовательность. Я не кодировал состояния, как это обычно лучше, так как я хотел сделать это другим способом (я видел подобный пример в книге, но код был на VHDL).

    При компиляции кода я получаю следующие ошибки.

    Я ничего не могу понять из сообщения об ошибке. Может кто-нибудь объяснить, пожалуйста, сообщение об ошибке и предложить, как его исправить?

    3 ответа

    В вашем блоке всегда отсутствуют ключевые слова начала и конца. Код думает, что вы пытаетесь создать экземпляр модуля, а не назначать сигналы. Только первая строка будет захвачена в блоке Always (назначение Q1). Другие не будут. Попробуй это:

    Как примечание, этот код действительно очень уродлив. Есть лучший способ сделать это??

    У вас есть несколько синтаксических ошибок.

    Тебе необходимо begin/end в вашем always блок.

    Даже после исправления у вас в коде все точки с запятой:

    По совпадению, это текущее назначение в моем классе разработки расширенной логики CPE166. Основная идея в задании — правильно синтезировать регистры. Примерно так (хотя наше назначение было намного сложнее с несколькими возможными входами, более длинными последовательностями, сбросом, программируемыми последовательностями и кнопками, которые нужно было разобрать):

    Это создаст 4-битный сдвиговый регистр, который будет сдвигаться на каждом положительном фронте тактового сигнала. Самое новое значение x_in будет введено с одной стороны, а самое старое значение x_in будет смещено. Текущие значения регистра сдвига постоянно сравниваются с параметром correct_sequence , который, когда истина, заставит y_out идти высоко.

    Источник

    • Источник

    My code is a sequential structure, 8 constant taps, 8 bit FIR. I used a memory to save all the input*taps, but I keep getting and error while trying to save these multiplications.

    I compiled it on Modelsim and got «syntax error». After, I tried iverilog and got «syntax error» and «error: Invalid module instantiation». I feel like I’m missing something really obvious but couldn’t solve it.

    The code goes as follows:

    /*  Código de um filtro FIR 8 taps, 8 bits
Aluno: Rafael Menezes
Start date: 19/07/2017

Modelo original - Sequencial ALTERNATIVO por reg+load
v1.5

BUG REPORT: 
    - Problema com a memória das multiplicações (linha 54);

NOTES:
    - Incrementador do sel é feito por always (linha 59);
    - Necessita, também, fazer o xor pro load (?);
*/

//código do fir
module fir(x,clk,rst,y);
input signed [8:0]x;                        //entrada do fir
input clk,rst;                              //clock e reset
output signed [16:0]y;                      //saída do fir
reg signed [16:0] m[0:7];                   //variáveis auxiliares para as multiplicações
wire signed [8:0]x1,x2,x3,x4,x5,x6,x7;      //variáveis auxiliares para os atrasos
wire signed [8:0]x_aux;                     //variável auxiliar para o atraso selecionado pelo mux
wire signed [8:0]h_aux;                     //variável auxiliar para o tap selecionado pelo mux
reg         [2:0]sel;                       //variável responsável pelo select do mux
parameter n=8;                              //parâmetro do loop das multiplicações

// valores pré-definidos dos taps
parameter signed h0=-4'd1;
parameter signed h1=4'd7;
parameter signed h2=-4'd2;
parameter signed h3=4'd5;
parameter signed h4=-4'd5;
parameter signed h5=4'd3;
parameter signed h6=4'd1;
parameter signed h7=4'd4;

    //atrasos
    ffd u1(clk,rst,x,x1);   //x[n-1]
    ffd u2(clk,rst,x1,x2);  //x[n-2]
    ffd u3(clk,rst,x2,x3);  //x[n-3]
    ffd u4(clk,rst,x3,x4);  //x[n-4]
    ffd u5(clk,rst,x4,x5);  //x[n-5]
    ffd u6(clk,rst,x5,x6);  //x[n-6]
    ffd u7(clk,rst,x6,x7);  //x[n-7]

genvar i;
generate
    for (i=0; i<n; i=i+1) begin: mux
    mux81 mux1(.clk(clk),.sel(sel),.in1(x),.in2(x1),.in3(x2),.in4(x3),
                    .in5(x4),.in6(x5),.in7(x6),.in8(x7),.out(x_aux));           //mux que seleciona as entradas
    mux81 mux2(.clk(clk),.sel(sel),.in1(h0),.in2(h1),.in3(h2),.in4(h3),
                    .in5(h4),.in6(h5),.in7(h6),.in8(h7),.out(h_aux));           //mux que seleiona os taps
    m[i]=x_aux*h_aux;       // THE ERROR IS RIGHT HERE!
    end
endgenerate

//rotina que incrementa o select a cada pulso de clock
always @(posedge clk) begin 
    if (sel==3'b111) begin
         sel <= 3'b000;
    end else begin
         sel <= sel + 3'b001;
    end
end

    assign y=m[0]+m[1]+m[2]+m[3]+m[4]+m[5]+m[6]+m[7];       

endmodule


//código do flip flop d que será usado como o integrador (atraso)
module ffd(clk,rst,in,out);
input clk,rst;
input signed [8:0]in;
output signed [8:0]out;
reg signed [8:0]out;

always @ (posedge clk) begin            //sembre na borda de subida verifica se o rst está ligado
    if(rst==1) begin                    //se não estiver ligado, atribui a entrada para a saída
        out<=0;
    end else begin
        out<=in;
    end
end

endmodule

//código mux para selecionar os taps e as entradas
module mux81(clk,sel,rst,in1,in2,in3,in4,in5,in6,in7,in8,out);
input signed [8:0]in1,in2,in3,in4,in5,in6,in7,in8;
input [2:0]sel;
input clk,rst;
output signed [8:0]out;
reg signed [8:0]out;

always @ (posedge clk or sel) begin
    if (rst==1) begin
        out<=0;
    end else if (sel==3'd0) begin
        out<=in1;
    end else if (sel==3'd1) begin
        out<=in2;
    end else if (sel==3'd2) begin
        out<=in3;
    end else if (sel==3'd3) begin
        out<=in4;
    end else if (sel==3'd4) begin
        out<=in5;
    end else if (sel==3'd5) begin
        out<=in6;
    end else if (sel==3'd6) begin
        out<=in7;
    end else if (sel==3'd7) begin
        out<=in8;
    end
end

endmodule

    Источник

    I have defined a module for a Mealy State Machine that detects a particular sequence. I haven’t encoded states as is usually a better choice as I wanted to do it the other way(I saw a similar example in a book, but the code was in VHDL).

    module seq_detector(y_out,Clk,x_in);
  output y_out;
  reg y_out;
  input x_in, Clk;
  reg Q1,Q2,Q3,Q4;
  always @(posedge Clk)
    Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
    Q2 <= ((!Q3)&&Q4;&&(!x_in))||(Q1&&Q2;&&(!Q3)&&(!Q4)&&x_in);
    Q3 <= Q1&&Q2;&&(!Q3)&&(x_in);
    Q4 <= (Q1&&Q2;&&(x_in))||(Q1&&(!Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(x_in))||((!Q1)&&(!Q3)&&Q4;&&x_in)||(Q1&&Q2;&&(!Q4)&&x_in);

  always @(x_in or Q1 or Q2 or Q3 or Q4)
  y_out <= Q3||(Q2&&(!Q4)&&x_in);
endmodule

    On compiling the code, I get the following errors. 

    mini_project.v:8: syntax error
mini_project.v:8: error: Invalid module instantiation
mini_project.v:9: error: Invalid module instantiation
mini_project.v:10: error: Invalid module instantiation

    I can’t make out anything of the error message. Can someone please explain the error message and suggest how to correct it ?

    3 Answers

    You are missing begin and end keywords in your always block. The code thinks that you are trying to instantiate a module rather than do signal assignments. Only the first line will be captured under the always block (the Q1 assignment). The others will not. Try this:

    always @(posedge Clk)
begin
  Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
  Q2 <= ((!Q3)&&Q4;&&(!x_in))||(Q1&&Q2;&&(!Q3)&&(!Q4)&&x_in);
  Q3 <= Q1&&Q2;&&(!Q3)&&(x_in);
  Q4 <= (Q1&&Q2;&&(x_in))||(Q1&&(!Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(x_in))||((!Q1)&&(!Q3)&&Q4;&&x_in)||(Q1&&Q2;&&(!Q4)&&x_in);
end

    As a side note, this code is really really really ugly. Is there a better way to do this??

    You have multiple syntax errors.

    You need a begin/end in your always block.

      always @(posedge Clk) begin
    Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
    Q2 <= ((!Q3)&&Q4;&&(!x_in))||(Q1&&Q2;&&(!Q3)&&(!Q4)&&x_in);
    Q3 <= Q1&&Q2;&&(!Q3)&&(x_in);
    Q4 <= (Q1&&Q2;&&(x_in))||(Q1&&(!Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(x_in))||((!Q1)&&(!Q3)&&Q4;&&x_in)||(Q1&&Q2;&&(!Q4)&&x_in);
  end

    Even after fixing that, you have stray semicolons all throughout your code:

    Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
// ---------------------------

    Coincidentally this is a current assignment in my CPE166 advanced logic design class. The main idea in the assignment is to synthesize registers correctly. Something like this (though our assignment was much more complicated with multiple possible inputs, longer sequences, reset, programmable sequences, and buttons which needed to be debounced):

    module sequence_detector(
input wire x_in,clk,
output wire y_out 
);

reg [3:0] seq, seq_nxt;

parameter correct_sequence = 4'b1001;

always @(posedge clk) 
    seq <= seq_nxt;

always @(*)
    seq_nxt = {seq[2:0] , x_in};

assign y_out = (seq == correct_sequence);
endmodule

    This will create a 4-bit shift register which will shift on every positive clock edge. The newest value of x_in will go in on one side and the oldest value of x_in will be shifted out. The current values of the shift register are constantly compared to the parameter correct_sequence, which when true will make y_out go high.

    Synthesized Logic

    Источник

    I can’t find documentation on running RV12 simulation with Icarus Verilog.
    I can only guess how to run iverilog simulation.

    Here is my command secuence under Debian Linux:

    $ iverilog -v
Icarus Verilog version 10.1 (stable) ()
...
$ git clone --recursive https://github.com/RoaLogic/RV12
$ cd RV12
RV12 $ make -C sim/ahb3lite/regression/bin  SIMULATORS=icarus TECHNOLOGY=generic icarus

    Here is output error log:

    make: Entering directory '/home/antony/RV12/sim/ahb3lite/regression/bin'
make[1]: Entering directory '/home/antony/RV12/sim/ahb3lite/regression/bin/icarus'
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:125: syntax error
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:125: error: invalid module item.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:126: error: port HSEL is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:127: error: port HADDR is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:128: error: port HWDATA is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:129: error: port HRDATA is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:130: error: port HWRITE is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:131: error: port HSIZE is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:132: error: port HBURST is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:133: error: port HPROT is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:134: error: port HTRANS is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:135: error: port HMASTLOCK is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:136: error: port HREADY is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:137: error: port HRESP is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:138: syntax error
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:143: error: invalid module item.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:146: syntax error
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:146: error: invalid module item.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:147: error: port HSEL is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:109: error: Port ``HSEL'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:148: error: port HADDR is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:110: error: Port ``HADDR'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:149: error: port HWDATA is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:111: error: Port ``HWDATA'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:150: error: port HRDATA is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:112: error: Port ``HRDATA'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:151: error: port HWRITE is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:113: error: Port ``HWRITE'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:152: error: port HSIZE is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:114: error: Port ``HSIZE'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:153: error: port HBURST is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:115: error: Port ``HBURST'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:154: error: port HPROT is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:116: error: Port ``HPROT'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:155: error: port HTRANS is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:117: error: Port ``HTRANS'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:156: error: port HMASTLOCK is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:118: error: Port ``HMASTLOCK'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:157: error: port HREADY is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:119: error: Port ``HREADY'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:158: error: port HREADYOUT is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:159: error: port HRESP is not in the port list.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:121: error: Port ``HRESP'' has already been declared a port.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:160: syntax error
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:165: error: invalid module item.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:242: sorry: modport task/function ports are not yet supported.
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:292: warning: task definition for "set_not_ready" has an empty port declaration list!
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:298: warning: task definition for "set_ready" has an empty port declaration list!
/home/antony/RV12/ahb3lite_pkg/rtl/verilog/ahb3lite_pkg.sv:304: warning: task definition for "set_error" has an empty port declaration list!
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:245: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:248: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:249: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:249: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:252: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:253: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:253: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:256: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:257: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:257: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:260: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:261: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:261: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:264: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:265: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:265: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:268: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:269: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:269: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:272: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:273: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_alu.sv:273: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:75: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:82: error: duplicate definition for localparam 'SBITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:84: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:85: error: duplicate declaration for net or variable 'func3' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:86: error: duplicate declaration for net or variable 'func7' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:87: error: duplicate declaration for net or variable 'is_rv64' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:179: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:182: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:183: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:183: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:184: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:184: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:185: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:186: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:187: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:193: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:194: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:194: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:195: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:195: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:196: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:196: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:197: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:197: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:198: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:198: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:199: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:199: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:200: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:200: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:201: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:201: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:202: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:202: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:203: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:203: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:204: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:204: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:205: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:211: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:212: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:212: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:213: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:221: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:222: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:222: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:223: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:223: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:224: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:224: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:225: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:225: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:226: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:226: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:227: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:227: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:228: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:228: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:229: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:229: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:230: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:230: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:231: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:231: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:232: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:232: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:233: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:238: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:239: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:239: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:240: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:240: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:241: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:241: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:242: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:242: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:243: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:249: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:250: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:250: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:251: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:251: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:252: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:252: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:253: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:253: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:254: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:254: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:255: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:255: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:256: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:256: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:257: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:257: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:258: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:263: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:264: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:264: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:265: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:265: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:266: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:266: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:267: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:277: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:288: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:290: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:291: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:291: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:292: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:292: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:293: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:293: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:294: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:294: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:295: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:295: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:296: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:296: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:297: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:297: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:298: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:302: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:306: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:308: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:309: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:309: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:310: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:310: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:311: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:311: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:312: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:313: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:313: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:314: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:319: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_lsu.sv:342: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:85: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:177: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:180: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:181: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:181: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:182: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:183: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:184: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:187: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:188: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:188: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:189: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:190: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:191: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:194: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:195: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:195: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:196: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:197: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:198: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:201: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:202: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:202: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:203: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:204: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:205: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:208: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:209: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:209: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:210: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:211: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:212: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:215: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:216: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:216: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:217: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:218: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:219: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:222: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:223: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:223: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:224: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:225: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:226: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:229: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:230: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:230: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:231: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:232: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:233: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:237: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:238: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:238: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:239: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:240: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:241: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:244: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:245: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:245: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:246: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:247: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:248: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:252: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:253: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:253: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:254: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:255: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:256: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:268: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:269: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:269: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:270: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:272: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:273: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:274: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:275: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:279: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:280: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:280: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:281: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:283: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:284: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:285: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:289: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:290: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:290: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:291: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:293: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:294: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:295: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:297: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:297: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:301: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_bu.sv:303: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:60: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:78: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:79: error: malformed statement
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:87: error: duplicate definition for function 'sext32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:123: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:124: error: duplicate declaration for net or variable 'func3' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:125: error: duplicate declaration for net or variable 'func7' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:129: error: duplicate declaration for net or variable 'opA32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:130: error: duplicate declaration for net or variable 'opB32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:142: error: duplicate declaration for net or variable 'state' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:180: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:182: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:183: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:183: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:184: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:184: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:185: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:190: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:191: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:191: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:192: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:192: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:193: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:193: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:194: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:199: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:200: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:200: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:201: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:201: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:202: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:202: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:203: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:203: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:204: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:204: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:205: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:209: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:297: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:298: Syntax in assignment statement l-value.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:299: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:299: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:300: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:300: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:301: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:309: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:310: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:310: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:311: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:311: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:312: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:313: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:313: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:314: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:314: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:315: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:321: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:322: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:322: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:324: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:325: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:329: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:331: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:337: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:338: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:338: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:342: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:343: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:343: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:345: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:346: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:351: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:352: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:354: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:355: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:355: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:357: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_mul.sv:358: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:61: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:66: error: duplicate definition for function 'sext32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:75: error: duplicate definition for function 'twos' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:82: error: duplicate definition for function 'abs' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:96: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:97: error: duplicate declaration for net or variable 'func3' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:98: error: duplicate declaration for net or variable 'func7' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:99: error: duplicate declaration for net or variable 'is_rv64' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:102: error: duplicate declaration for net or variable 'opA32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:103: error: duplicate declaration for net or variable 'opB32' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:105: error: duplicate declaration for net or variable 'cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:121: error: duplicate declaration for net or variable 'state' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:197: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:200: Syntax in assignment statement l-value.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:201: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:223: error: Incomprehensible case expression.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:380: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:381: Syntax in assignment statement l-value.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:400: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:401: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:402: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:402: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:403: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:406: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:407: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:407: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:408: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:408: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:409: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:409: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:410: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:410: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:411: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:411: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:412: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:412: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:413: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:413: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:414: syntax error
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:414: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/ex/riscv_div.sv:415: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:126: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:137: error: duplicate declaration for net or variable 'alu_r' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:143: error: duplicate declaration for net or variable 'alu_bubble' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:189: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:191: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:192: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:192: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:193: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:193: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:194: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:194: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:195: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:199: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:200: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:200: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:201: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:201: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:202: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:202: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:203: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:214: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:277: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:279: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:280: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:280: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:281: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:281: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:282: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:282: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:283: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:290: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:292: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:292: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:293: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:294: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_ex.sv:295: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:112: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:131: error: duplicate declaration for net or variable 'ex_opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:137: error: duplicate declaration for net or variable 'is_rv64' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:268: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:271: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:272: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:272: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:273: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:273: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:274: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:274: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:275: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:275: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:276: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:276: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:277: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:277: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:278: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:278: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:279: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:279: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:280: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:280: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:281: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:281: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:282: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:282: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:283: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:291: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:292: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:292: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:295: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:296: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:296: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:299: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:300: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:300: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:303: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:304: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:304: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:307: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:308: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:308: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:311: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:312: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:315: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:316: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:316: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:319: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:320: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:320: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:323: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:324: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:324: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:327: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:328: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:328: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:331: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:332: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:332: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:335: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:336: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:336: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:346: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:347: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:347: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:348: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:349: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:350: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:350: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:353: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:354: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:354: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:357: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:358: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:358: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:361: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:362: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:362: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:365: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:366: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:366: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:368: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:369: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:369: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:370: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:371: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:372: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:372: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:375: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:376: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:376: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:379: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:380: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:380: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:382: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:383: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:383: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:384: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:384: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:385: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:385: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:386: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:386: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:387: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:388: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:389: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:389: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:392: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:393: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:393: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:396: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:397: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:397: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:400: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:401: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:401: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:413: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:414: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:414: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:415: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:415: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:416: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:416: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:417: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:417: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:418: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:418: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:419: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:419: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:420: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:420: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:421: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:421: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:422: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:422: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:423: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:423: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:424: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:424: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:425: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:430: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:431: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:431: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:432: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:432: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:433: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:433: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:434: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:434: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:435: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:435: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:436: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:436: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:437: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:437: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:438: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:438: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:439: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:439: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:440: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:440: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:441: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:441: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:442: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:455: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:456: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:456: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:458: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:459: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:462: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:463: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:463: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:465: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:466: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:469: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:470: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:470: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:472: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:473: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:476: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:477: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:477: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:479: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:480: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:483: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:484: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:484: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:486: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:487: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:490: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:491: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:491: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:493: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:494: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:497: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:498: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:498: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:500: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:501: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:504: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:505: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:505: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:507: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:508: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:511: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:512: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:512: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:514: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:515: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:518: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:519: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:519: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:521: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:522: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:531: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:532: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:532: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:548: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:548: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:555: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:557: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:558: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:558: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:559: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:559: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:560: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:566: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:567: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:567: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:568: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:568: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:569: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:569: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:570: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:570: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:571: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:571: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:572: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:572: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:573: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:573: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:574: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:577: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:578: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:578: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:579: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:579: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:580: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:580: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:581: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:581: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:582: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:582: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:583: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:583: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:584: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:584: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:585: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:585: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:586: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:586: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:587: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:587: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:588: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:588: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:589: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:589: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:590: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:590: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:591: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:591: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:592: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:592: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:593: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:593: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:594: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:594: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:595: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:595: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:596: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:596: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:597: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:597: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:598: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:598: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:599: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:599: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:600: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:600: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:601: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:601: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:602: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:602: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:603: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:603: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:604: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:604: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:605: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:605: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:606: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:606: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:607: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:607: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:608: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:608: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:609: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:609: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:610: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:610: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:611: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:611: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:612: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:612: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:613: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:613: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:614: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:614: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:617: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:617: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:618: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:618: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:619: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:619: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:620: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:620: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:621: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:621: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:622: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:622: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:624: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:624: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:625: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:631: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:632: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:632: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:633: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:633: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:634: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:634: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:635: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:635: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:636: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:636: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:637: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:637: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:638: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:638: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:639: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:639: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:640: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:640: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:641: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:641: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:644: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:644: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:645: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:651: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:652: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:652: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:653: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:653: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:654: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:654: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:655: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:655: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:656: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:656: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:657: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:657: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:658: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:658: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:659: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:659: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:660: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:660: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:661: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:661: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:662: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:662: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:663: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:663: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:664: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:664: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:665: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:673: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:674: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:674: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:675: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:675: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:676: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:676: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:677: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:677: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:678: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:678: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:679: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:679: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:680: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:680: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:681: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:681: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:682: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:682: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:683: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:683: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:684: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:684: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:685: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:685: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:686: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:686: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:688: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:688: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:689: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:689: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:690: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:690: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:692: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:692: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:693: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:693: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:694: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:694: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:695: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:695: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:696: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:696: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:697: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:697: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:698: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:698: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:699: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:699: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:700: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:700: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:701: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:701: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:702: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:702: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:704: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:704: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:705: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:705: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:706: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:706: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:707: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:707: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:708: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:708: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:709: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:709: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:710: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:710: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:711: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:711: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:712: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:712: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:713: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:713: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:715: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:715: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:716: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:716: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:717: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:717: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:718: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:718: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:719: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:719: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:720: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:720: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:721: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:721: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:722: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:722: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:723: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:723: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:724: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:724: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:725: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:725: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:726: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:726: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:727: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:727: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:728: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:728: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:729: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:729: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:730: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:730: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:731: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:731: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:732: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:732: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:733: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:733: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:734: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:734: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:735: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:735: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:737: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:737: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:738: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:742: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:743: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:743: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:744: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:744: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:745: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:745: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:746: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:746: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:747: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:747: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:748: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:748: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:749: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:749: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:750: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:750: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:751: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:751: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:752: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:752: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:753: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:753: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:754: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:754: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:755: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:755: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:757: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:757: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:758: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:758: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:759: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:759: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:761: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:761: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:762: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:762: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:763: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:763: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:764: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:764: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:765: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:765: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:766: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:766: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:767: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:767: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:768: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:768: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:769: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:769: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:770: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:770: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:771: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:771: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:773: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:773: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:774: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:774: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:775: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:775: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:776: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:776: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:777: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:777: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:778: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:778: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:779: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:779: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:780: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:780: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:781: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:781: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:782: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:782: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:784: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:784: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:785: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:785: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:786: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:786: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:787: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:787: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:788: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:788: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:789: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:789: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:790: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:790: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:791: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:791: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:792: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:792: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:793: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:793: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:794: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:794: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:795: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:795: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:796: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:796: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:797: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:797: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:798: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:798: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:799: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:799: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:800: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:800: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:801: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:801: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:802: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:802: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:803: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:803: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:804: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:804: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:805: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:805: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:806: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:806: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:807: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:807: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:809: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:809: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:810: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:810: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:812: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:812: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_id.sv:813: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:78: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:106: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:219: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:221: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:222: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:222: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:223: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:223: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:224: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:228: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:229: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:229: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:230: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:230: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:249: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:253: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:254: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:254: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:259: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:260: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:260: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:263: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:264: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:264: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:269: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:270: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:270: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_if.sv:303: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:70: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:77: error: duplicate declaration for net or variable 'opcode' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:78: error: duplicate declaration for net or variable 'func3' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:79: error: duplicate declaration for net or variable 'func7' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:83: error: duplicate declaration for net or variable 'mem_data' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:84: error: duplicate declaration for net or variable 'mem_qb' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:85: error: duplicate declaration for net or variable 'mem_qh' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:86: error: duplicate declaration for net or variable 'mem_qw' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_memwb.sv:184: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:68: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:126: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:117: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:222: error: duplicate declaration for net or variable 'is_rv64' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:223: error: duplicate declaration for net or variable 'has_rvc' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:227: error: duplicate declaration for net or variable 'has_muldiv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:228: error: duplicate declaration for net or variable 'has_amo' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:291: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:298: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:299: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:299: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:300: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:300: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:301: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:301: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:302: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:302: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:303: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:303: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:304: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:304: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:305: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:305: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:307: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:307: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:308: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:308: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:309: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:309: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:310: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:310: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:311: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:311: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:312: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:313: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:313: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:314: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:314: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:315: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:315: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:318: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:331: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:332: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:332: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:333: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:333: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:334: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:334: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:335: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:335: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:336: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:336: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:337: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:337: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:338: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:338: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:339: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:339: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:340: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:340: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:341: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:341: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:344: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:360: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:361: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:361: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:362: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:362: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:363: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:363: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:364: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:364: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:365: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:365: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:366: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:366: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:367: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:367: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:368: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:368: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:369: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:369: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:372: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:372: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:373: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:373: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:374: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:374: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:375: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:375: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:376: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:376: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:377: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:396: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:397: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:397: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:398: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:398: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:399: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:399: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:400: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:400: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:401: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:401: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:402: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:402: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:403: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:403: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:404: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:404: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:405: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:405: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:406: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:406: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:407: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:407: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:408: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:408: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:409: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:409: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:410: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:410: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:411: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:411: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:412: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:412: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:413: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:413: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:414: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:414: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:415: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:415: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:416: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:416: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:418: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:418: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:419: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:425: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:426: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:426: error: syntax error in continuous assignment
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:900: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:902: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:903: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:903: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:904: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:904: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:905: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:905: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:906: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:906: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:907: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:907: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:908: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:908: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:909: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:909: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:910: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:910: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:911: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:911: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:912: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:912: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:913: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:913: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:914: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:914: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:915: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:920: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:937: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:939: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:940: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:940: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:941: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:941: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:942: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:942: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:943: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:943: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:944: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:944: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:945: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:945: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:946: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:946: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:947: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:947: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:948: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:948: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:949: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:949: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:950: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:950: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:951: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:951: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:952: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:954: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_state1.9.sv:1280: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_bp.sv:67: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_bp.sv:141: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:94: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:229: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:231: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:232: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:232: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:233: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:233: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:234: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:234: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:236: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:236: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:237: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:237: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:239: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:239: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:240: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:240: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:242: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:242: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:243: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:243: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:245: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:245: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:246: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:246: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:248: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:248: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:249: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:249: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:251: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:251: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:252: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:252: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:254: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:254: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:255: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:255: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:257: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:257: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:258: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:258: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:260: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:260: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:261: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:265: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:266: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:266: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:267: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:267: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:268: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:268: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:269: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:269: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:270: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:270: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:271: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:271: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:272: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:283: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:284: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:284: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:288: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:289: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:289: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:297: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:298: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:298: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:302: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:303: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:303: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:307: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:308: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:308: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:312: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:312: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:312: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:312: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:319: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:320: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:320: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:321: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:323: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:325: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:331: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:332: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:332: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:391: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:396: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:413: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:416: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:417: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:430: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:438: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:445: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:446: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:448: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:449: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:449: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:450: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:450: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:451: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:451: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:457: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:457: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:458: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:463: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_du.sv:464: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:124: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:149: error: duplicate declaration for net or variable 'ex_bubble' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:154: error: duplicate declaration for net or variable 'du_flush' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:158: error: duplicate declaration for net or variable 'wb_stall' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:159: error: duplicate declaration for net or variable 'du_stall' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:170: error: duplicate declaration for net or variable 'bu_bp_update' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:194: error: duplicate declaration for net or variable 'ex_memadr' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:206: error: duplicate declaration for net or variable 'ex_csr_reg' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:207: error: duplicate declaration for net or variable 'ex_csr_wval' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:209: error: duplicate declaration for net or variable 'ex_csr_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:212: error: duplicate declaration for net or variable 'wb_dst' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:224: error: duplicate declaration for net or variable 'du_dati_rf' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:227: error: duplicate declaration for net or variable 'du_ie' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:228: error: duplicate declaration for net or variable 'du_exceptions' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/riscv_core.sv:394: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w.sv:64: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w.sv:141: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:62: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:68: error: genvar 'i' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:85:        the previous declaration is here.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:82: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:87: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:88: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:92: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:93: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:102: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_generic.sv:103: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:63: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:66: error: genvar 'i' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:85:        the previous declaration is here.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:70: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:72: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:73: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:107: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3x.sv:108: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:63: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:69: error: duplicate declaration for net or variable 'biten' in 'riscv_alu'.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:70: error: genvar 'i' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:85:        the previous declaration is here.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:73: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:75: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:76: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:129: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:130: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:162: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1r1w_easic_n3xs.sv:163: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw.sv:59: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw.sv:92: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:58: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:64: error: genvar 'i' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_rf.sv:85:        the previous declaration is here.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:66: error: duplicate declaration for net or variable 'mem_array' in 'riscv_alu'.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:77: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:82: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:83: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:87: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:88: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:95: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_generic.sv:96: syntax error
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_easic_n3x.sv:58: error: invalid module item.
/home/antony/RV12/memory/rtl/verilog/rl_ram_1rw_easic_n3x.sv:80: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:53: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:60: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:62: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:63: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:63: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:64: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:64: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:65: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:65: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:66: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:66: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:67: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:67: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:68: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:68: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:69: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:69: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:70: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:75: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:76: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:76: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:77: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:77: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:78: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:78: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:79: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:79: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:80: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:80: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:81: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:81: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:82: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:82: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:83: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:83: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:84: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:84: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:85: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:85: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:86: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:86: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:87: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:88: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:88: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:89: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:89: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:90: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:90: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:91: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:96: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:97: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:97: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_memmisaligned.sv:98: syntax error
/home/antony/RV12/rtl/verilog/core/riscv_wbuf.sv:68: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/riscv_wbuf.sv:243: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:151: error: Typedef identifier "fifo_struct" is already a type name.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:158: error: genvar 'way' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_wbuf.sv:101:        the previous declaration is here.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:198: error: duplicate declaration for net or variable 'cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:246: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:263: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:291: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:297: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:389: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:392: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:393: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:394: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:395: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:401: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:401: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:401: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:401: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:406: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:407: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:408: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:411: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:416: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:423: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:425: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:426: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:426: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:427: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:427: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:428: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:430: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:455: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:459: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:462: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:465: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:468: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:472: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:479: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:493: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:494: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:494: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:496: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:498: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:500: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:505: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:506: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:506: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:508: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:510: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:511: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:515: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:517: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:517: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:518: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:519: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:520: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:524: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:525: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:525: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:526: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:527: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:528: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:534: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:535: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:535: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:564: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:565: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:566: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:568: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:569: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:569: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:570: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:570: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:571: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:574: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_icache_core.sv:699: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:77: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:100: error: Typedef identifier "fifo_struct" is already a type name.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:107: error: duplicate declaration for net or variable 'is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:109: error: duplicate declaration for net or variable 'biu_stb_cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:110: error: duplicate declaration for net or variable 'biu_fifo' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:111: error: duplicate declaration for net or variable 'if_flush_dly' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_noicache_core.sv:284: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:92: error: duplicate definition for localparam 'SETS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:93: error: duplicate definition for localparam 'BLK_OFF_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:94: error: duplicate definition for localparam 'IDX_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:95: error: duplicate definition for localparam 'TAG_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:96: error: duplicate definition for localparam 'LRU_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:97: error: duplicate definition for localparam 'BLK_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:98: error: duplicate definition for localparam 'BURST_SIZE' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:99: error: duplicate definition for localparam 'BURST_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:100: error: duplicate definition for localparam 'BURST_OFF' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:101: error: duplicate definition for localparam 'BURST_LSB' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:104: error: duplicate definition for localparam 'DAT_ABITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:105: error: duplicate definition for localparam 'DAT_IDX_LSB' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:106: error: duplicate definition for localparam 'DAT_IDX_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:117: error: duplicate definition for function 'onehot2int' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:127: error: duplicate definition for function 'new_lru' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:157: error: Typedef identifier "tag_struct" is already a type name.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:158: error: duplicate definition for localparam 'TAG_STRUCT_BITS' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:165: error: genvar 'way' has already been declared.
/home/antony/RV12/rtl/verilog/core/riscv_wbuf.sv:101:        the previous declaration is here.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:166: error: duplicate declaration for net or variable 'n' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:171: error: duplicate declaration for net or variable 'is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:190: error: duplicate declaration for net or variable 'tag_widx' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:192: error: duplicate declaration for net or variable 'dat_widx' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:193: error: duplicate declaration for net or variable 'core_tag' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:196: error: duplicate declaration for net or variable 'way_hit' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:199: error: duplicate declaration for net or variable 'way_dat' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:200: error: duplicate declaration for net or variable 'tag_re' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:201: error: duplicate declaration for net or variable 'tag_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:202: error: duplicate declaration for net or variable 'dat_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:203: error: duplicate declaration for net or variable 'dat_in' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:204: error: duplicate declaration for net or variable 'dat_out' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:205: error: duplicate declaration for net or variable 'dat_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:206: error: duplicate declaration for net or variable 'tag_in' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:207: error: duplicate declaration for net or variable 'tag_out' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:214: error: duplicate declaration for net or variable 'cache_hit' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:215: error: duplicate declaration for net or variable 'dcache_hit' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:217: error: duplicate declaration for net or variable 'cache_dat' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:220: error: duplicate declaration for net or variable 'way_random' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:221: error: duplicate declaration for net or variable 'fill_way_select' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:222: error: duplicate declaration for net or variable 'fill_way_select_rnd' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:224: error: duplicate declaration for net or variable 'state' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:225: error: duplicate declaration for net or variable 'hold_bu_cacheflush' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:226: error: duplicate declaration for net or variable 'flushing' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:227: error: duplicate declaration for net or variable 'filling' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:230: error: duplicate declaration for net or variable 'cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:230: error: duplicate declaration for net or variable 'nxt_cnt' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:300: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:317: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:347: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:353: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:595: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:598: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:599: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:600: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:601: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:606: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:615: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:620: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:621: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:627: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:640: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:643: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:644: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:645: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:646: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:647: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:648: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:648: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:649: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:649: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:650: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:650: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:651: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:651: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:652: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:652: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:653: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:653: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:654: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:658: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:661: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:663: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:664: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:664: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:665: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:675: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:682: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:684: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:685: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:687: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:688: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:688: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:689: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:689: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:690: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:690: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:691: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:691: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:692: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:693: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:694: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:694: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:695: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:700: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:701: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:701: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:702: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:702: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:703: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:703: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:704: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:704: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:705: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:709: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:721: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:727: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:728: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:729: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:730: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:731: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:732: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:736: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:736: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:736: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:736: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:744: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:747: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:753: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:757: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:764: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:776: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:777: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:778: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:779: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:779: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:780: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:780: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:781: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:786: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:787: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:787: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:788: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:788: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:789: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:789: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:790: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:790: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:792: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:792: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:793: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:793: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:794: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:798: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:799: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:799: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:828: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:830: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:831: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:831: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:832: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:832: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:833: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:833: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:834: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:838: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:884: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:892: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:893: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:893: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:894: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:898: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:899: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:899: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:900: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:905: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:906: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:906: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:908: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:914: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:915: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:915: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:916: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:920: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:921: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:921: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:923: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:928: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:929: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:929: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:930: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:935: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:936: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:936: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:937: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:943: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:944: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:944: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:946: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:951: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:952: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:952: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:953: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:957: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:958: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:958: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:959: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1034: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1035: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1037: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1038: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1038: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1039: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1039: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1040: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1045: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1045: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1045: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1045: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1047: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1048: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1049: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1049: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1049: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1049: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1052: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1054: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1055: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1059: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1060: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1062: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1063: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1063: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1064: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1064: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1065: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1068: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1069: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1071: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1072: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1072: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1073: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1073: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1074: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1080: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1085: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1089: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1090: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1090: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1094: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1095: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1095: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1099: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1100: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1100: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1104: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1105: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1105: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1109: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1110: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1110: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1115: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1116: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1116: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1120: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1121: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1121: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1125: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1126: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1126: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1130: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1131: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1131: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1135: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1136: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1136: error: Invalid module instantiation
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1144: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1152: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1157: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1158: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1160: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1161: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1161: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1162: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1162: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_dcache_core.sv:1163: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:77: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:89: error: duplicate declaration for net or variable 'state' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:91: error: duplicate declaration for net or variable 'is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:213: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:215: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:216: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:216: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:217: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:217: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:218: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:218: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:219: syntax error
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:221: error: invalid module item.
/home/antony/RV12/rtl/verilog/core/cache/riscv_nodcache_core.sv:234: syntax error
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_cache_biu_ahb3lite.sv:78: error: invalid module item.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_cache_biu_ahb3lite.sv:278: syntax error
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:101: error: duplicate declaration for net or variable 'biu_stb' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:102: error: duplicate declaration for net or variable 'biu_stb_ack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:104: error: duplicate declaration for net or variable 'biu_adri' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:105: error: duplicate declaration for net or variable 'biu_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:106: error: duplicate declaration for net or variable 'biu_type' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:107: error: duplicate declaration for net or variable 'biu_lock' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:108: error: duplicate declaration for net or variable 'biu_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:109: error: duplicate declaration for net or variable 'biu_di' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:110: error: duplicate declaration for net or variable 'biu_do' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:111: error: duplicate declaration for net or variable 'biu_rack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:114: error: duplicate declaration for net or variable 'biu_is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:115: error: duplicate declaration for net or variable 'biu_is_instruction' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:116: error: duplicate declaration for net or variable 'biu_prv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_icache_ahb3lite.sv:189: syntax error
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:87: error: invalid module item.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:105: error: duplicate declaration for net or variable 'cache_req' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:107: error: duplicate declaration for net or variable 'cache_adr' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:108: error: duplicate declaration for net or variable 'cache_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:109: error: duplicate declaration for net or variable 'cache_d' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:111: error: duplicate declaration for net or variable 'cache_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:112: error: duplicate declaration for net or variable 'cache_prv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:113: error: duplicate declaration for net or variable 'cache_flush' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:116: error: duplicate declaration for net or variable 'biu_stb' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:117: error: duplicate declaration for net or variable 'biu_stb_ack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:118: error: duplicate declaration for net or variable 'biu_adro' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:119: error: duplicate declaration for net or variable 'biu_adri' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:120: error: duplicate declaration for net or variable 'biu_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:121: error: duplicate declaration for net or variable 'biu_type' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:122: error: duplicate declaration for net or variable 'biu_lock' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:123: error: duplicate declaration for net or variable 'biu_we' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:124: error: duplicate declaration for net or variable 'biu_di' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:125: error: duplicate declaration for net or variable 'biu_do' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:126: error: duplicate declaration for net or variable 'biu_wack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:127: error: duplicate declaration for net or variable 'biu_rack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:128: error: duplicate declaration for net or variable 'biu_err' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:130: error: duplicate declaration for net or variable 'biu_is_cacheable' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:131: error: duplicate declaration for net or variable 'biu_is_instruction' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:132: error: duplicate declaration for net or variable 'biu_prv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_dcache_ahb3lite.sv:286: syntax error
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:73: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:74: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:75: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:76: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:77: warning: extra digits given for sized hex constant.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:134: error: invalid module item.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:143: error: duplicate declaration for net or variable 'if_stall_nxt_pc' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:145: error: duplicate declaration for net or variable 'if_stall' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:146: error: duplicate declaration for net or variable 'if_flush' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:147: error: duplicate declaration for net or variable 'if_parcel' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:148: error: duplicate declaration for net or variable 'if_parcel_pc' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:149: error: duplicate declaration for net or variable 'if_parcel_valid' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:150: error: duplicate declaration for net or variable 'if_parcel_misaligned' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:153: error: duplicate declaration for net or variable 'mem_req' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:154: error: duplicate declaration for net or variable 'mem_ack' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:155: error: duplicate declaration for net or variable 'mem_adr' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:157: error: duplicate declaration for net or variable 'mem_q' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:159: error: duplicate declaration for net or variable 'mem_be' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:160: error: duplicate declaration for net or variable 'mem_misaligned' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:163: error: duplicate declaration for net or variable 'st_prv' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:166: error: duplicate declaration for net or variable 'dcflush_rdy' in 'riscv_alu'.
/home/antony/RV12/rtl/verilog/ahb3lite/riscv_top_ahb3lite.sv:290: syntax error
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:41: error: invalid module item.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:44: error: duplicate definition for parameter 'XLEN' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:80: error: duplicate declaration for net or variable 'HCLK' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:80: error: duplicate declaration for net or variable 'HRESETn' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:83: error: duplicate declaration for net or variable 'ins_HSEL' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:84: error: duplicate declaration for net or variable 'ins_HADDR' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:85: error: duplicate declaration for net or variable 'ins_HRDATA' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:86: error: duplicate declaration for net or variable 'ins_HWDATA' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:87: error: duplicate declaration for net or variable 'ins_HWRITE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:88: error: duplicate declaration for net or variable 'ins_HSIZE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:89: error: duplicate declaration for net or variable 'ins_HBURST' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:90: error: duplicate declaration for net or variable 'ins_HPROT' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:91: error: duplicate declaration for net or variable 'ins_HTRANS' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:92: error: duplicate declaration for net or variable 'ins_HMASTLOCK' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:93: error: duplicate declaration for net or variable 'ins_HREADY' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:94: error: duplicate declaration for net or variable 'ins_HRESP' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:97: error: duplicate declaration for net or variable 'dat_HSEL' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:98: error: duplicate declaration for net or variable 'dat_HADDR' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:99: error: duplicate declaration for net or variable 'dat_HWDATA' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:100: error: duplicate declaration for net or variable 'dat_HRDATA' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:101: error: duplicate declaration for net or variable 'dat_HWRITE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:102: error: duplicate declaration for net or variable 'dat_HSIZE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:103: error: duplicate declaration for net or variable 'dat_HBURST' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:104: error: duplicate declaration for net or variable 'dat_HPROT' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:105: error: duplicate declaration for net or variable 'dat_HTRANS' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:106: error: duplicate declaration for net or variable 'dat_HMASTLOCK' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:107: error: duplicate declaration for net or variable 'dat_HREADY' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:108: error: duplicate declaration for net or variable 'dat_HRESP' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:114: error: duplicate declaration for net or variable 'dbg_ack' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:339: syntax error
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:365: error: invalid module item.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:374: error: duplicate declaration for net or variable 'dHWRITE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:456: syntax error
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:475: error: invalid module item.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:476: error: duplicate definition for function 'hostcode_to_string' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:486: error: duplicate declaration for net or variable 'watchdog_cnt' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/testbench_top.sv:514: syntax error
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:66: error: invalid module item.
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:92: error: duplicate declaration for net or variable 'mem_array' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:104: error: duplicate declaration for net or variable 'dHTRANS' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:105: error: duplicate declaration for net or variable 'dHWRITE' in 'riscv_alu'.
/home/antony/RV12/bench/verilog/ahb3lite/memory_model_ahb3lite.sv:119: syntax error
ivl: parse.y:2010: int VLparse(): Assertion `current_task == 0' failed.
Aborted
Makefile:60: recipe for target 'testbench_top.out' failed
make[1]: *** [testbench_top.out] Error 134
make[1]: Leaving directory '/home/antony/RV12/sim/ahb3lite/regression/bin/icarus'
Makefile:251: recipe for target 'icarus' failed
make: *** [icarus] Error 2
make: Leaving directory '/home/antony/RV12/sim/ahb3lite/regression/bin'
    Источник

    The bugs are listed here can be reproduced on tests for Verilog Translator project (so called «ieee-tests»).

  • test_03_08_01_1.v 
    test_03_08_01_1.v:25: syntax error
test_03_08_01_1.v:27: error: malformed statement
test_03_08_01_1.v:28: syntax error
test_03_08_01_1.v:33: error: malformed statement
test_03_08_01_1.v:34: syntax error
test_03_08_01_1.v:39: error: malformed statement
test_03_08_01_1.v:40: syntax error

    Cause: attributes for «case» statement branches like «(* full_case, parallel_case *)» are unsupported.

  • test_03_08_01_2.v 
    test_03_08_01_2.v:25: syntax error
test_03_08_01_2.v:27: error: malformed statement
test_03_08_01_2.v:28: syntax error
test_03_08_01_2.v:32: error: malformed statement
test_03_08_01_2.v:33: syntax error

    Cause: attributes for «case» statement branches like «(* full_case *)» are unsupported.

  • test_03_08_01_6.v 
    test_03_08_01_6.v:25: syntax error
test_03_08_01_6.v:25: error: malformed statement

    Cause: attributes for assignments like «a = b + (* mode = «cla» *) c;» are unsupported.

  • test_03_08_01_7.v 
    test_03_08_01_7.v:25: syntax error
test_03_08_01_7.v:25: error: malformed statement

    Cause: attributes for assignments like «a = add (* mode = «cla» *) (b, c);» are unsupported.

  • test_03_08_01_8.v 
    test_03_08_01_8.v:25: syntax error
test_03_08_01_8.v:25: error: malformed statement

    Cause: attributes for assignments like «a = b ? (* no_glitch *) c : d;» are unsupported.

  • test_04_03_01_1.v 
    test_04_03_01_1.v:24: sorry: trireg nets not supported.

    Cause: cannot parse «trireg (small) storeit;»

  • test_04_03_02_1.v 
    test_04_03_02_1.v:22: syntax error
test_04_03_02_1.v:22: error: invalid module item.
test_04_03_02_1.v:23: syntax error
test_04_03_02_1.v:23: error: invalid module item.

    Cause: cannot parse «tri1 scalared [63:0] bus64;»

  • test_04_04_01_1.v 
    test_04_04_01_1.v:22: sorry: trireg nets not supported.
test_04_04_01_1.v:23: sorry: trireg nets not supported.
test_04_04_01_1.v:25: syntax error
test_04_04_01_1.v:25: error: invalid module item.

    Cause: cannot parse «trireg a;»

  • test_04_09_03_1_1.v 
    test_04_09_03_1_1.v:26: sorry: only 1 dimensional arrays are currently supported.
test_04_09_03_1_1.v:28: sorry: only 1 dimensional arrays are currently supported.

    Cause: cannot parse «reg arrayb[7:0][0:255];»

  • test_04_09_03_1_2.v 
    test_04_09_03_1_2.v:26: sorry: only 1 dimensional arrays are currently supported.
test_04_09_03_1_2.v:28: sorry: only 1 dimensional arrays are currently supported.

    Cause: cannot parse «reg arrayb[7:0][0:255];»

  • test_04_10_03_2.v 
    test_04_10_03_2.v:23: syntax error
test_04_10_03_2.v:23: error: invalid module item.
test_04_10_03_2.v:24: syntax error
test_04_10_03_2.v:24: error: invalid module item.

    Cause: the «specparam» is unsupported.

  • test_05_01_14_1.v 
    test_05_01_14_1.v:30: error: Array b['sd3:'sd0] cannot be indexed by a range.

    Cause: cannot parse «result = {a, b[3:0], w, 3’b101};»

  • test_05_02_01_4.v 
    test_05_02_01_4.v:54: error: Unable to bind wire/reg/memory `x' in `test'
test_05_02_01_4.v:58: error: Unable to bind wire/reg/memory `z' in `test'

    Cause: cannot parse «addr = x;»

  • test_05_02_02_2.v 
    test_05_02_02_2.v:25: sorry: only 1 dimensional arrays are currently supported.
test_05_02_02_2.v:26: sorry: only 1 dimensional arrays are currently supported.

    Cause: cnnot parse «wire threed_array[0:255][0:255][0:7];»

  • test_05_03_00_1.v 
    test_05_03_00_1.v:25: warning: choosing typ expression.

    Cause: «parameter val = (32’d 50: 32’d 75: 32’d 100);»

  • test_06_01_03_1.v 
    test_06_01_03_1.v:24: sorry: net delays not supported.

    Cause: «wire #10 wireA;»

  • test_07_14_01_1.v 
    test_07_14_01_1.v:25: warning: choosing typ expression.
test_07_14_01_1.v:25: warning: choosing typ expression.
test_07_14_01_1.v:25: warning: choosing typ expression.
test_07_14_01_1.v:26: warning: choosing typ expression.
test_07_14_01_1.v:26: warning: choosing typ expression.
test_07_14_01_1.v:26: warning: choosing typ expression.

    Cause: «bufif0 #(5:7:9, 8:10:12, 15:18:21) b1 (io1, io2, dir);»

  • test_07_14_01_2.v 
    test_07_14_01_2.v:26: warning: choosing typ expression.
test_07_14_01_2.v:27: warning: choosing typ expression.

    Cause: » #(95:100:105) clk = 1;»

  • test_07_14_02_2_1.v 
    test_07_14_02_2_1.v:25: sorry: trireg nets not supported.

    Cause: «trireg ( large ) #(0,0,50) cap1;»

  • test_07_14_02_2_2.v 
    test_07_14_02_2_2.v:26: sorry: trireg nets not supported.

    Cause: «trireg ( large ) #(0,0,50) cap1;»

  • test_08_06_00_1.v 
    test_08_06_00_1.v:46: syntax error
test_08_06_00_1.v:46: error: syntax error in parameter value assignment list.
test_08_06_00_1.v:46: error: Invalid module instantiation
*Cause*: "d_edge_ff #p3 d_inst (q, clock, data);"
  • test_08_07_00_1.v 
    test_08_07_00_1.v:30: syntax error

    Cause: » ? ?? 01 : ? : 1 ;»

  • test_09_06_00_1.v 
    test_09_06_00_1.v:27: syntax error
test_09_06_00_1.v:28: error: invalid module item.
test_09_06_00_1.v:29: syntax error
test_09_06_00_1.v:29: error: Invalid module instantiation
test_09_06_00_1.v:30: error: Invalid module instantiation
test_09_06_00_1.v:31: error: Invalid module instantiation
test_09_06_00_1.v:34: error: invalid module item.
test_09_06_00_1.v:35: syntax error
test_09_06_00_1.v:35: error: Invalid module instantiation
test_09_06_00_1.v:36: error: Invalid module instantiation

    Cause: «begin : mult»

  • test_09_06_00_2.v 
    test_09_06_00_2.v:23: syntax error
test_09_06_00_2.v:24: error: invalid module item.
test_09_06_00_2.v:25: syntax error
test_09_06_00_2.v:25: error: Invalid module instantiation
test_09_06_00_2.v:26: error: Invalid module instantiation
test_09_06_00_2.v:29: error: invalid module item.
test_09_06_00_2.v:30: syntax error
test_09_06_00_2.v:30: error: Invalid module instantiation

    Cause: «begin : count1s»

  • test_09_07_05_4.v 
    test_09_07_05_4.v:33: internal error: NetProc::nex_input not implemented

    Cause: «* // equivalent to (c or d)
    x = c ^ d;»

  • test_09_07_07_1.v 
    test_09_07_07_1.v:32: syntax error

    Cause: «repeat (-3) @ (posedge clk)»

  • test_10_03_00_5.v 
    test_10_03_00_5.v:44: syntax error
test_10_03_00_5.v:45: error: malformed statement
test_10_03_00_5.v:48: syntax error
test_10_03_00_5.v:49: error: malformed statement

    Cause: «begin : posedge(clk)»

  • test_12_02_00_1.v 
    test_12_02_00_1.v:57: error: Range expressions must be constant.
test_12_02_00_1.v:57       : This MSB expression violates the rule: LOG2(DEPTH)

    Cause: «reg [LOG2:0] depth;»

  • test_12_03_07_1.v 
    test_12_03_07_1.v:29: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
test_12_03_07_1.v:26: error: no wire/reg net_r in module driver.
test_12_03_07_1.v:33: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
test_12_03_07_1.v:32: error: no wire/reg net_r in module receiver.
test_12_03_07_1.v:29: error: Net net_r is not defined in this context.
test_12_03_07_1.v:36: error: Unable to bind wire/reg/memory `net_r' in `receiver'

    Cause:

    26: module driver (net_r);
27:   output net_r;
28:   real r;
29:   wire [64:1] net_r = $realtobits(r);
30: endmodule
31: 
32: module receiver (net_r);
33:   input net_r;
34:   wire [64:1] net_r;
35:   real r;
36:   initial assign r = $bitstoreal (net_r);
37: endmodule
  • test_12_04_02_1.v 
    test_12_04_02_1.v:46: syntax error
test_12_04_02_1.v:46: error: invalid module item.

    Cause: «else;»

  • test_14_03_00_1.v 
    test_14_03_00_1.v:30: warning: choosing typ expression.
test_14_03_00_1.v:30: warning: choosing typ expression.
test_14_03_00_1.v:31: warning: choosing typ expression.
test_14_03_00_1.v:31: warning: choosing typ expression.

    Cause:

    specparam  tRise_clk_q = 45:150:270, tFall_clk_q=60:200:350;
specparam  tRise_Control = 35:40:45, tFall_control=40:50:65;
  • test_14_03_01_1.v 
    test_14_03_01_1.v:29: syntax error
test_14_03_01_1.v:26: error: syntax error in specify block

    Cause:

    (C => Q) = 20;
(C => Q) = 10:14:20;
  • test_15_05_00_2.v 
    test_15_05_00_2.v:58: warning: choosing typ expression.
test_15_05_00_2.v:58: warning: choosing typ expression.
test_15_05_00_2.v:59: warning: choosing typ expression.
test_15_05_00_2.v:59: warning: choosing typ expression.

    Cause:

    specparam tPLHc = 4:6:9, tPHLc = 5:8:11;
specparam tPLHpc = 3:5:6, tPHLpc = 4:7:9;
  • test_15_05_01_3.v 
    test_15_05_01_3.v:32: warning: timing checks are not supported and delayed signal "del_CLK" will not be driven.
test_15_05_01_3.v:32: warning: timing checks are not supported and delayed signal "del_DATA1" will not be driven.

    Cause:

    $setuphold (posedge CLK, DATA1, -10, 20,,,, del_CLK, del_DATA1);
  • test_15_05_01_4.v 
    test_15_05_01_4.v:30: syntax error
test_15_05_01_4.v:30: Invalid simple path
test_15_05_01_4.v:31: warning: timing checks are not supported and delayed signal "dCLK" will not be driven.
test_15_05_01_4.v:31: warning: timing checks are not supported and delayed signal "dD" will not be driven.
test_15_05_01_4.v:32: warning: timing checks are not supported and delayed signal "dCLK" will not be driven.
test_15_05_01_4.v:32: warning: timing checks are not supported and delayed signal "dD" will not be driven.

    Cause:

    (CLK = Q) = 6;
$setuphold (posedge CLK, posedge D, -3,  8, , , , dCLK, dD);
$setuphold (posedge CLK, negedge D, -7, 13, , , , dCLK, dD);
  • test_15_05_02_3.v 
    test_15_05_02_3.v:33: warning: timing checks are not supported and delayed signal "dCP" will not be driven.
test_15_05_02_3.v:33: warning: timing checks are not supported and delayed signal "dD" will not be driven.
test_15_05_02_3.v:34: warning: timing checks are not supported and delayed signal "dCP" will not be driven.
test_15_05_02_3.v:34: warning: timing checks are not supported and delayed signal "dTI" will not be driven.
test_15_05_02_3.v:35: warning: timing checks are not supported and delayed signal "dCP" will not be driven.
test_15_05_02_3.v:35: warning: timing checks are not supported and delayed signal "dTE" will not be driven.

    Cause:

    $setuphold(posedge CP, D, -10,  20, notifier, ,TE_cond_D,  dCP, dD);
$setuphold(posedge CP, TI, 20, -10, notifier, ,TE_cond_TI, dCP, dTI);
$setuphold(posedge CP, TE, -4,   8, notifier, ,DXTI_cond,  dCP, dTE);
  • test_15_07_00_1.v 
    test_15_07_00_1.v:29: error: Q is not a valid l-value in DFF.
test_15_07_00_1.v:26:      : Q is declared here as wire.

    Cause:

    module DFF (Q, CLK, DAT);
  input CLK;
  input [7:0] DAT;
  output [7:0] Q;

  always @(posedge clk)
    Q = DAT;
  specify
    $setup (DAT, posedge CLK, 10);
  endspecify
endmodule
  • test_16_02_03_1.v 
    test_16_02_03_1.v:25: syntax error
test_16_02_03_1.v:25: error: invalid module item.
test_16_02_03_1.v:35: syntax error
test_16_02_03_1.v:35: error: invalid module item.

    Cause:

    22:module clock(clk);
23:  output clk;
24:  reg clk;
25:  specparam dhigh=0, dlow=0;
26:
27:  initial clk = 0;
28:
29:  always
30:    begin
31:      #dhigh clk = 1; // Clock remains low for time dlow
32:                      // before transitioning to 1
33:      #dlow  clk = 0; // Clock remains high for time dhigh
34:                      // before transitioning to 0
35:    end;
36:endmodule
  • test_17_02_04_4_1.v 
    test_17_02_04_4_1.v:40: syntax error
test_17_02_04_4_1.v:40: error: malformed statement

    Cause:

    code = $fread (mem, fd, , count);
  • test_17_05_01_1.v 
    test_17_05_01_1.v:31: syntax error
test_17_05_01_1.v:31: error: invalid module item.
test_17_05_01_1.v:34: syntax error
test_17_05_01_1.v:34: error: invalid module item.
test_17_05_01_1.v:37: syntax error
test_17_05_01_1.v:37: error: invalid module item.

    Cause:

    $async$and$array (mem, {a1,a2,a3,a4,a5,a6,a7}, {b1,b2,b3});

// is equivalent
$async$and$array (mem, awire, breg);

// An example of a synchronous system call is as follows
$sync$or$plane (mem, {a1,a2,a3,a4,a5,a6,a7}, {b1,b2,b3});
  • 17_05_02_1.v 
    test_17_05_02_1.v:28: syntax error
test_17_05_02_1.v:28: error: invalid module item.
test_17_05_02_1.v:31: syntax error
test_17_05_02_1.v:31: error: invalid module item.

    Cause:

    $async$nor$plane (mem,{a1,a2,a3,a4,a5,a6,a7},{b1,b2,b3});

// An example of a nand plane system call is as follows:
$sync$nand$plane (mem,{a1,a2,a3,a4,a5,a6,a7}, {b1,b2,b3});
  • test_17_08_00_1.v 
    test_17_08_00_1.v:26: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
test_17_08_00_1.v:31: error: Scalar port ``net_r'' has a vectored net declaration [64:1].
test_17_08_00_1.v:33: error: Unable to bind wire/reg/memory `net_r' in `receiver'

    Cause:

    23: module driver (net_r);
24:   output net_r;
25:   real r;
26:   wire [64:1] net_r = $realtobits (r);
27: endmodule
28: 
29: module receiver (net_r);
30:   input net_r;
31:   wire [64:1] net_r;
32:   real r;
33:   initial assign r = $bitstoreal (net_r);
34: endmodule
    • Источник

    When I try to write a testbench for the up5k usb_uart coding, Why do I have so many declaration errors ??

    [phung@archlinux usb]$ iverilog -o usb_tb *.v
    ./../util.v:26: error: function declarations must be contained within a module.
    usb_fs_in_arb.v:35: Module usb_fs_in_arb was already declared here: ./usb_fs_in_arb.v:1

    usb_fs_in_pe.v:403: Module usb_fs_in_pe was already declared here: ./usb_fs_in_pe.v:2

    usb_fs_out_arb.v:25: Module usb_fs_out_arb was already declared here: ./usb_fs_out_arb.v:1

    usb_fs_out_pe.v:411: Module usb_fs_out_pe was already declared here: ./usb_fs_out_pe.v:2

    ./usb_fs_in_arb.v:35: Module usb_fs_in_arb was already declared here: ./usb_fs_in_arb.v:1

    ./usb_fs_in_pe.v:403: Module usb_fs_in_pe was already declared here: ./usb_fs_in_pe.v:2

    ./usb_fs_out_arb.v:25: Module usb_fs_out_arb was already declared here: ./usb_fs_out_arb.v:1

    ./usb_fs_out_pe.v:411: Module usb_fs_out_pe was already declared here: ./usb_fs_out_pe.v:2

    ./usb_fs_tx.v:267: Module usb_fs_tx was already declared here: ./usb_fs_tx.v:3

    ./usb_fs_tx_mux.v:16: Module usb_fs_tx_mux was already declared here: ./usb_fs_tx_mux.v:1

    ./usb_fs_rx.v:392: Module usb_fs_rx was already declared here: ./usb_fs_rx.v:3

    usb_fs_pe.v:244: Module usb_fs_pe was already declared here: ./usb_fs_pe.v:9

    usb_fs_rx.v:392: Module usb_fs_rx was already declared here: ./usb_fs_rx.v:3

    usb_fs_tx_mux.v:16: Module usb_fs_tx_mux was already declared here: ./usb_fs_tx_mux.v:1

    usb_fs_tx.v:267: Module usb_fs_tx was already declared here: ./usb_fs_tx.v:3

    usb_serial_ctrl_ep.v:468: Module usb_serial_ctrl_ep was already declared here: ./usb_serial_ctrl_ep.v:3

    usb_serial_ep.v:118: Module usb_serial_ep was already declared here: ./usb_serial_ep.v:1

    ./usb_fs_in_arb.v:35: Module usb_fs_in_arb was already declared here: ./usb_fs_in_arb.v:1

    ./usb_fs_in_pe.v:403: Module usb_fs_in_pe was already declared here: ./usb_fs_in_pe.v:2

    ./usb_fs_out_arb.v:25: Module usb_fs_out_arb was already declared here: ./usb_fs_out_arb.v:1

    ./usb_fs_out_pe.v:411: Module usb_fs_out_pe was already declared here: ./usb_fs_out_pe.v:2

    ./usb_fs_tx.v:267: Module usb_fs_tx was already declared here: ./usb_fs_tx.v:3

    ./usb_fs_tx_mux.v:16: Module usb_fs_tx_mux was already declared here: ./usb_fs_tx_mux.v:1

    ./usb_fs_rx.v:392: Module usb_fs_rx was already declared here: ./usb_fs_rx.v:3

    ./usb_fs_pe.v:244: Module usb_fs_pe was already declared here: ./usb_fs_pe.v:9

    ./usb_serial_ctrl_ep.v:468: Module usb_serial_ctrl_ep was already declared here: ./usb_serial_ctrl_ep.v:3

    ./usb_serial_ep.v:118: Module usb_serial_ep was already declared here: ./usb_serial_ep.v:1

    usb_serial.v:233: Module usb_serial was already declared here: ./usb_serial.v:5

    usb_tb.v:33: syntax error
    usb_tb.v:17: error: Invalid module instantiation
    usb_tb.v:35: error: invalid module item.
    usb_tb.v:36: syntax error
    usb_tb.v:40: error: invalid module item.
    usb_tb.v:41: syntax error
    usb_tb.v:41: error: Invalid module instantiation
    usb_tb.v:42: error: Invalid module instantiation
    usb_tb.v:43: error: Invalid module instantiation
    usb_tb.v:44: error: Invalid module instantiation
    usb_tb.v:46: error: invalid module item.
    usb_tb.v:47: syntax error
    usb_tb.v:47: error: Invalid module instantiation
    usb_tb.v:49: error: invalid module item.
    usb_tb.v:50: syntax error
    usb_tb.v:50: error: Invalid module instantiation
    usb_tb.v:52: error: invalid module item.
    usb_tb.v:53: syntax error
    usb_tb.v:53: error: Invalid module instantiation
    usb_tb.v:55: error: invalid module item.
    usb_tb.v:56: syntax error
    usb_tb.v:58: error: invalid module item.
    ./usb_fs_in_arb.v:35: Module usb_fs_in_arb was already declared here: ./usb_fs_in_arb.v:1

    ./usb_fs_in_pe.v:403: Module usb_fs_in_pe was already declared here: ./usb_fs_in_pe.v:2

    ./usb_fs_out_arb.v:25: Module usb_fs_out_arb was already declared here: ./usb_fs_out_arb.v:1

    ./usb_fs_out_pe.v:411: Module usb_fs_out_pe was already declared here: ./usb_fs_out_pe.v:2

    ./usb_fs_tx.v:267: Module usb_fs_tx was already declared here: ./usb_fs_tx.v:3

    ./usb_fs_tx_mux.v:16: Module usb_fs_tx_mux was already declared here: ./usb_fs_tx_mux.v:1

    ./usb_fs_rx.v:392: Module usb_fs_rx was already declared here: ./usb_fs_rx.v:3

    ./usb_fs_pe.v:244: Module usb_fs_pe was already declared here: ./usb_fs_pe.v:9

    ./usb_serial_ctrl_ep.v:468: Module usb_serial_ctrl_ep was already declared here: ./usb_serial_ctrl_ep.v:3

    ./usb_serial_ep.v:118: Module usb_serial_ep was already declared here: ./usb_serial_ep.v:1

    ./usb_serial.v:233: Module usb_serial was already declared here: ./usb_serial.v:5

    [phung@archlinux usb]$

    module usb_tb();

    reg clk, clk_48mhz;
    reg reset;

    wire pin_usbp, pin_usbn;
    wire pin_pu;

    wire [7:0] rx_data;
    wire rx_strobe;
    reg [7:0] tx_data;
    reg tx_strobe;

    assign pin_usbp = tx_strobe ?  tx_data : 1'bz;
    assign pin_usbn = tx_strobe ? !tx_data : 1'bz;

    usb_uart dut
    (
    .clk(clk),
    .clk_48mhz(clk_48mhz),
    .reset(reset),

    .pin_usbp(pin_usbp),
    .pin_usbn(pin_usbn),
    .pin_pu(pin_pu),

    .rx_data(rx_data),
    .rx_strobe(rx_strobe),
    .tx_data(tx_data),
    .tx_strobe(tx_strobe)
    )

    initial begin
      $dumpfile("usb_tb.vcd");
      $dumpvars(1);
    end

    initial
    begin
    clk = 0;
    clk_48mhz = 0;
    reset = 0;
    tx_data = 0;
    tx_strobe = 1;

    @(posedge clk);
    tx_data = 1;

    @(posedge clk);
    tx_data = 2;

    @(posedge clk);
    tx_data = 3;

    #50 $finish;
    end

    always #5  clk =  ! clk;
    always #10  clk_48mhz =  ! clk_48mhz;

    endmodule

    Источник

    Я пытаюсь создать 32-битный массив с 10 пробелами в Verilog. Вот код:

    reg [31:0] internalMemory [0:9];

    Затем я пытаюсь присвоить 32-битные значения разным местам внутри этого регистра. Вот пример кода:

    internalMemory[0] = 32'b00000000001000100001100000100000;
internalMemory[1] = 32'b00000000001000100001100000100001;

    При компиляции я получаю следующую ошибку:

    IR.v:21: syntax error
IR.v:21: error: Invalid module instantiation

    Эта строка 21 представляет мою попытку доступа к internalMemory[1].

    Любые советы относительно того, почему это происходит и как это исправить?

    Благодарность!

    ОБНОВЛЕНИЕ 1:

    В соответствии с запросом здесь есть код для регистра инструкций, который я пытаюсь реализовать:

    `include "IRTester.v"
module instruction_register(IREnable, programCounter, controlUnit, RS, RT, RD, immediate);

parameter  dataWidth = 32; //input size

input wire IREnable;
input wire  [31:0] programCounter; //instruction to be read
output wire [5:0] controlUnit;
output wire [4:0] RS;
output wire [4:0] RT;
output wire [4:0] RD;
output wire [15:0] immediate;


wire [31:0] temp;
reg [31:0] internalMemory [0:9];

always @ (posedge IREnable)

    internalMemory[0] = 32'b00000000001000100001100000100000;
    internalMemory[1] = 32'b00000000001000100001100000100001;

    assign temp = internalMemory[programCounter];
    assign controlUnit = temp[31:26];
    assign RS = temp[25:21];
    assign RT = temp[20:16];
    assign RD = temp[15:11];
    assign immediate = temp[15:0];

endmodule

    3 ответа

    Вы должны использовать начало/конец

    always @ (posedge IREnable) begin
    internalMemory[0] = 32'b00000000001000100001100000100000;
    internalMemory[1] = 32'b00000000001000100001100000100001;
end


    0

    XjR
    16 Апр 2015 в 08:57 

        always @ (posedge IREnable)

    internalMemory[0] = 32'b00000000001000100001100000100000;
    internalMemory[1] = 32'b00000000001000100001100000100001;

    assign temp = internalMemory[programCounter];
    assign controlUnit = temp[31:26];
    assign RS = temp[25:21];
    assign RT = temp[20:16];
    assign RD = temp[15:11];
    assign immediate = temp[15:0];

endmodule

    В этом коде вы закодировали блок always без каких-либо begin - end. так что, когда вы выполняете код, строка, следующая за always ( internalMemory[0] = 32'b00000000001000100001100000100000; ), будет считаться в блоке always; как поведенческий. вот почему следующая строка показывает ошибку, так как предполагается, что она находится в потоке данных.

    .


    0

    Roshan
    22 Апр 2015 в 23:22

    Вы не можете использовать операторы assign внутри блока always. Вытащите их.


    -1

    andi99
    16 Апр 2015 в 22:02

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