Error loading design quartus - Исправление ошибок и поиск оптимальных решений проблем

Hi everyone,

First I want to say that I searched all the threads here, and while this is a common problem, I could not figure out how to solve it.

I am trying to use a small testbench I wrote using the Quartus testbench template writer, but I am getting this error:

** Error: (vsim-3170) Could not find 'C:/Users/nettek/QuartusProjects/Final Project - 11.3.16 - par/test/simulation/modelsim/rtl_work.tb_test1'.# # Error loading design# Error: Error loading design# Pausing macro execution# MACRO ./Test_run_msim_rtl_vhdl.do PAUSED at line 14

Steps I took:

1. Created a BDF file with two components in it, obviously it has input/output ports and some internal signals.

2. Created an HDL file from the BDF file. Added it to project. Removed the BDF file from project (did not delete it).

3. Created a testbench using the Quartus template writer.

4. Added the VHT file to project.

5. Took to Assignments -> Settings -> EDA tool settings -> Simulation ->

Chose compile test bench and chose the VHT file.

6. Tools -> Run simulation tool -> RTL simulation which opened Modelsim.

Of course I always made sure to compile whenever I needed to.

I don’t understand this problem, just two days ago it didn’t happen and now it does. What could be the problem?

Also, I would appreciate if you could tell me how to test internal signals of a BDF file in Modelsim using a testbench. I know that I can give the signals names, turn the BDF file into a HDL file and then compile it in Modelsim, and then force the signals, but I want to use a testbench to make this be automatic. Problem is, using a testbench, I only see the input/outputs.

Thank you!

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Содержание

Verilog error loading design
ModelSim-Altera Error loading design
Verilog error loading design
ModelSim-Altera Error loading design
Verilog error loading design
ModelSim-Altera Error loading design
Verilog error loading design
Unable to run simulation in Simulation Waveform Editor
Modelsim error:error loading design #264
Comments
vsim -do «source tcl_files/run.tcl;»
Start time: 10:37:33 on Dec 12,2018
** Note: (vsim-3812) Design is being optimized.
** Error: /export/homeO5/yzhou/Documents/pulpino/vsim/..//tb/tb.sv(388): Can’t have packed array of integer type.
** Error: /export/homeO5/yzhou/Documents/pulpino/vsim/..//tb/tb.sv(388): Vopt Compiler exiting
** Error: (vopt-2064) Compiler back-end code generation process terminated with code 211.
** Note: (vopt-143) Recognized 1 FSM in architecture body «uart_receiver(rtl)».
** Note: (vopt-143) Recognized 1 FSM in module «axi_BW_allocator(fast)».
Error loading design
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This is my first time using ModelSim and writing testbenches, so this may sound like a silly problem. But I am having problems simulating my project on ModelSim from Quartus II. Here is the testbench I have written up for the project:

timing_gen_block mytiming_gen(reset, IN_4ms, CLK_IN, OUT_4ms, OUT_1ms, OUT_20KHZ, LOST_SINK);

initial // Clock generator

forever# 8 CLK_IN = !CLK_IN;

initial // Test stimulus

IN_4ms = 1;# 5 reset = 1;# 250 IN_4ms = 0;

$monitor($stime,, reset,, IN_4ms,, CLK_IN);

Now this compiles just fine. But when I try to simulate it in ModelSim from Quartus II by selecting tools > run eda simulation tool > eda rtl simulation , I get the following output in ModelSim:

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Verilog error loading design

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timing_gen_block mytiming_gen(reset, IN_4ms, CLK_IN, OUT_4ms, OUT_1ms, OUT_20KHZ, LOST_SINK);

initial // Clock generator

forever# 8 CLK_IN = !CLK_IN;

initial // Test stimulus

IN_4ms = 1;# 5 reset = 1;# 250 IN_4ms = 0;

$monitor($stime,, reset,, IN_4ms,, CLK_IN);

Now this compiles just fine. But when I try to simulate it in ModelSim from Quartus II by selecting tools > run eda simulation tool > eda rtl simulation , I get the following output in ModelSim:

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Verilog error loading design

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timing_gen_block mytiming_gen(reset, IN_4ms, CLK_IN, OUT_4ms, OUT_1ms, OUT_20KHZ, LOST_SINK);

initial // Clock generator

forever# 8 CLK_IN = !CLK_IN;

initial // Test stimulus

IN_4ms = 1;# 5 reset = 1;# 250 IN_4ms = 0;

$monitor($stime,, reset,, IN_4ms,, CLK_IN);

Now this compiles just fine. But when I try to simulate it in ModelSim from Quartus II by selecting tools > run eda simulation tool > eda rtl simulation , I get the following output in ModelSim:

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Verilog error loading design

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Unable to run simulation in Simulation Waveform Editor

Unable to run simulation in Simulation Waveform Editor

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Hello, I’m just starting to use Quartus for VHDL designs and I keep running into a problem while trying to run a simulation using a .vwf file in the Simulation Waveform Editor. Whenever my design infers a higher level component (such as the altsyncram in my example), I am unable to run a functional or a timing simulation without receiving the following error:

# ** Error: (vsim-3033) nofile(37): Instantiation of ‘generic_m10k’ failed. The design unit was not found.# # Region: /sim_tester_vlg_vec_tst/i1/ram_rtl_0|auto_generated|ram_block1a0 # Searched libraries:# C:/altera/13.1/modelsim_ase/altera/verilog/cyclonev# C:/altera/13.1/modelsim_ase/altera/verilog/altera# C:/altera/13.1/modelsim_ase/altera/verilog/altera_mf# C:/altera/13.1/modelsim_ase/altera/verilog/220model# C:/altera/13.1/modelsim_ase/altera/vhdl/sgate# C:/altera/13.1/modelsim_ase/altera/verilog/cyclonev# Loading work.sim_tester_vlg_sample_tst# Loading work.sim_tester_vlg_check_tst# Error loading design

Error loading design

I wrote some simple code to use to try to figure this error out. The VHDL code I am using is as follows:

library IEEE; use IEEE.std_logic_1164.all; entity sim_tester is port(in1: in std_logic_vector(7 downto 0); clk, r_en, w_en: in std_logic; out1: out std_logic_vector(7 downto 0)); end sim_tester; architecture sim of sim_tester is type MemoryType is array(0 to 15) of std_logic_vector(7 downto 0); signal ram: MemoryType := (others => (others => ‘0’)); signal w_addr: integer range 0 to 15 := 0; signal r_addr: integer range 0 to 15 := 0; begin process(clk) begin if clk’event and clk = ‘1’ then if r_en = ‘1’ then out1

From the error message, it seems like Quartus is not including all the libraries it needs when invoking Modelsim to do the simulation. I am not sure if that is an accurate observation, so help solving this in any direction would be greatly appreciated. I also attached the full log I received when attempting the simulation — this file includes the error message.

My Quartus set up is:

Quartus II 64-bit Version 13.1.1 Build 166 11/26/2013 SJ Web Edition

The simulation settings use ModelSim-Altera Version 10.1d

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im like a dirty piglet always ask for help and never share so today decided to wash my sins. inside modelsim on a library window if you would expand all the libraries and then click ctrl+f and type there «generic_m10k» you would find that it is located into altera_insim_ver library. so go to the project window in modelsim and right click on empty space then add to project -> existed file. navigate into altera13.1modelsim_asealteraverilogsrc and find altera_lnsim.v file, add it to your current project. compile it along with other files that you are using. now,in modelsim go to simulate -> start simulation ->library ->add and type: altera_lnsim_ver click ok. this way you are telling modelsim to use this library you just compiled. personally i think it should be programmed so that libraries you compile must be automatically included into the use list but by unknown reasons developers left this for us to do. remember, to learn it i have spent tens of hours, tens of days, and tens of neurons when i was nervous because nothing worked, so mention my name in prayers when you go to the church 🙂 tell the big guy i demand at least 1million to be happy :)))

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Modelsim error:error loading design #264

I just want to run helloworld test, I chose cmake_configure.riscv.gcc.sh , and the steps what I do is as same as what README.md told me. The error happened at the last step:
anyone has the same question?or someone help me ,thanks a lot.
ps:I’m new oneo(╥﹏╥)o

The text was updated successfully, but these errors were encountered:

The contents of modelsim transcription are as follows ：
source tcl_files/run.tcl

vsim -do «source tcl_files/run.tcl;»

Start time: 10:37:33 on Dec 12,2018

** Note: (vsim-3812) Design is being optimized.

** Error: /export/homeO5/yzhou/Documents/pulpino/vsim/..//tb/tb.sv(388): Can’t have packed array of integer type.

** Error: /export/homeO5/yzhou/Documents/pulpino/vsim/..//tb/tb.sv(388): Vopt Compiler exiting

** Error: (vopt-2064) Compiler back-end code generation process terminated with code 211.

** Note: (vopt-143) Recognized 1 FSM in architecture body «uart_receiver(rtl)».

** Note: (vopt-143) Recognized 1 FSM in module «axi_BW_allocator(fast)».

Error loading design

this is the result after I added VERBOSE=1 . maybe it’s more clear

** Error: /export/homeO5/yzhou/Documents/pulpino/vsim/..//tb/tb.sv(388): Can’t have packed array of integer type.

Fix your testbench.

@quangdaovu the code I did not find packed array of integer type. what is more ,line 388 is the end of the code. I think it may be not associated to the code.

I found it. at pulpino-1/tb/mem_dpi.svh,
buffer[i] = rdata_temp_arr[j][ 7:0];
buffer[i+1] = rdata_temp_arr[j][15:8];
buffer[i+2] = rdata_temp_arr[j][23:16];
buffer[i+3] = rdata_temp_arr[j][31:24];
error happened here.
The following is what I modified:
automatic logic [31:0] xxx_tmp=rdata_temp_arr[j];
buffer[i]= xxx_tmp[7:0];
buffer[i+1]=xxx_tmp[15:8];
buffer[i+2]=xxx_tmp[23:16];
buffer[i+3]=xxx_tmp[31:24];
//buffer[i] = rdata_temp_arr[j][ 7:0];
//buffer[i+1] = rdata_temp_arr[j][15:8];
//buffer[i+2] = rdata_temp_arr[j][23:16];
//buffer[i+3] = rdata_temp_arr[j][31:24];
and then,there is «helloworld» in console.But I don’t know the reason why the error happened.
If you know the reason,tell me please.Thanks!

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Источник

26.10.2020, 11:01. Показов 2484. Ответов 1

При моделировании в среде, ModelSim выдает ошибку: # Error loading design

Мой код:

Код

`timescale 10ns/100ps
module Verilog1;
wire [7:0]out;
reg [2:0]pin;
lab_1 g1(pin,out);
initial
begin
pin[1]=1'b0; pin[2]=1'b0; pin[3]=1'b0;
#3 pin[1]=1'b0; pin[2]=1'b0; pin[3]=1'b1;
#3 pin[1]=1'b0; pin[2]=1'b1; pin[3]=1'b0;
#3 pin[1]=1'b1; pin[2]=1'b0; pin[3]=1'b0;
#3 pin[1]=1'b0; pin[2]=1'b1; pin[3]=1'b1;
#3 pin[1]=1'b1; pin[2]=1'b1; pin[3]=1'b0;
#3 pin[1]=1'b1; pin[2]=1'b0; pin[3]=1'b1;
#3 pin[1]=1'b1; pin[2]=1'b1; pin[3]=1'b1;
end
initial
#50 $stop;
endmodule

Моя ошибка:
# Reading C:/altera/10.0/modelsim_ase/tcl/vsim/pref.tcl
# do lab_1_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying C:altera10.0modelsim_asewin32aloem/../modelsim.ini to
modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied
C:altera10.0modelsim_asewin32aloem/../modelsim.ini to modelsim.ini.
# Updated modelsim.ini.
#
# vlog -vlog01compat -work work +incdir+C:/altera/labs
{C:/altera/labs/lab_1.v}
# Model Technology ModelSim ALTERA vlog 6.5e Compiler 2010.02 Feb 27
2010
# — Compiling module lab_1
#
# Top level modules:
# lab_1
#
# vlog -vlog01compat -work work +incdir+C:/altera/labs
{C:/altera/labs/Verilog1.v}
# Model Technology ModelSim ALTERA vlog 6.5e Compiler 2010.02 Feb 27
2010
# — Compiling module Verilog1
# ** Warning: C:/altera/labs/Verilog1.v(8): [BSOB] — Bit-select into
‘pin’ is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(9): [BSOB] — Bit-select into
‘pin’ is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(10): [BSOB] — Bit-select into
‘pin’ is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(11): [BSOB] — Bit-select into
‘pin’ is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(12): [BSOB] — Bit-select into
‘pin’ is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(13): [BSOB] — Bit-select into
‘pin’ is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(14): [BSOB] — Bit-select into
‘pin’ is out of bounds.
# ** Warning: C:/altera/labs/Verilog1.v(15): [BSOB] — Bit-select into
‘pin’ is out of bounds.
#
# Top level modules:
# Verilog1
#
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L
cycloneive_ver -L rtl_work -L work -voptargs=»+acc» 50
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L
cycloneive_ver -L rtl_work -L work -voptargs=»+acc» -t 1ps 50
# ** Error: (vsim-3170) Could not find
‘C:alteralabssimulationmodelsimrtl_work.50’.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./lab_1_run_msim_rtl_verilog.do PAUSED at line 12

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Источник

I’m designing a Master-Slave D Flip Flop implementation in ModelSim. After compiling (Compile > Compile All), I’m typing vsim into the console, and the only error thrown is

# vsim
# Start time: [time]
# Error loading design

Is there any way of having vsim be more verbose with what is going wrong? Or, alternately, could someone tell me what I’m doing wrong?

For reference, my code is below:

methods.v

module dFlipFlop(
    D,
    Clk,
    En,
    Q
);

input D, Clk, En;
output Q;
reg Q;

always @ (posedge Clk)
if(~En) begin
    Q <= 1'b0;
end else begin
    Q <= D;
end

endmodule

module masterSlaveDFF(
    D,
    Clk,
    En,
    Q
);

input D, Clk, En;
output Q;

wire Y, inClk;

assign inClk = ~Clk;

dFlipFlop first (.D(D), .Clk(Clk), .En(En), .Q(Y));
dFlipFlop second (.D(Y), .Clk(inClk), .En(En), .Q(Q));

endmodule

dflipflop.v (My Testbench)

`include "methods.v"

module masterSlaveTest();

reg D, Clk, En, Q;

initial begin
    $monitor(D, Clk, En, Q);

    D = 1;
    Clk = 1;
    En = 0;

    #5 $finish;
end

always begin
    #5 Clk = ~Clk;
end

endmodule

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Article ID: 000079785

Content Type: Troubleshooting

Last Reviewed: 10/12/2011

# FATAL ERROR while loading design during simulation using Mentor Graphics ModelSim-Altera

Environment

Quartus Edition

Quartus® II Subscription Edition

Version Found: 11.0

FPGA Intellectual Property

Version Found: 11.0

BUILT IN — ARTICLE INTRO SECOND COMPONENT

Description

If you attempt to simulate, using the Mentor Graphics ModelSim-Altera
software, a VHDL design that contains a Low Latency PHY megafunction
with a 10 Gbps datapath, simulation fails with errors similar to
the following:

# ** Fatal: Error occurred in protected context. # Time: 0 ps Iteration: 0 Instance: /test_tst/test_inst/test_inst/<protected>/<protected>/<protected> File: nofile # FATAL ERROR while loading design # Error loading design

Description

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Источник

I’m new to modelsim and Verilog and I have got an error in it:

#         Region: /seqdectorTB
# Error loading design

1.3.v:

module myseqdetector(x,clk,reset,y);
  input x,clk,reset;
  output reg y;
  reg[2:0] ps,ns;
  always@(posedge clk)
  begin
    if(reset)begin
      ps<=2'b00;
    end
    else begin
     ps<=ns;
    end
  end
  always@(ps or x)
  begin
    case(ps)
      3'b000 : ns = x? 3'b000 : 3'b001;
      3'b001 : ns = x? 3'b010 : 3'b001;
      3'b010 : ns = x? 3'b000 : 3'b011;
      3'b011 : ns = x? 3'b100 : 3'b001;
      3'b100 : ns = x? 3'b000 : 3'b101;
      3'b101 : ns = x? 3'b100 : 3'b110;
      3'b110 : ns = x? 3'b010 : 3'b001;
    endcase
  end
  always@(ps or x)
  begin
    case(ps)
      3'b000 :y = 1'b0;
      3'b001 :y = 1'b0;
      3'b010 :y = 1'b0;
      3'b011 :y = 1'b0;
      3'b100 :y = 1'b0;
      3'b101 :y = 1'b0;
      3'b110 :y = 1'b1;
    endcase
  end
endmodule




my testbench 1.3tb.v:
module seqdectorTB();
  parameter clkperiod=100;
  reg x,clk,reset;
  wire y;
  myseqdetector(x,clk,reset,y);

  initial begin
   clk = 0;
   forever #100 clk = ~clk;
  end
  initial begin
    reset=1;
    #101 x=1;
    #201 x=0;
    #301 x=1;
    #401 x=0;
    #501 x=1;
    #601 x=1;
    #701 x=0;
    #801 x=1;
    #901 x=0;
    #1010 x=1;
    #1101 x=0;
  end
endmodule

thanks all

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Closed

wooolf0455 opened this issue

Dec 12, 2018

· 5 comments

Comments

The contents of modelsim transcription are as follows ：
source tcl_files/run.tcl

vsim -do «source tcl_files/run.tcl;»

Start time: 10:37:33 on Dec 12,2018

** Note: (vsim-3812) Design is being optimized…

** Error: /export/homeO5/yzhou/Documents/pulpino/vsim/..//tb/tb.sv(388): Can’t have packed array of integer type.

** Error: /export/homeO5/yzhou/Documents/pulpino/vsim/..//tb/tb.sv(388): Vopt Compiler exiting

** Error: (vopt-2064) Compiler back-end code generation process terminated with code 211.

** Note: (vopt-143) Recognized 1 FSM in architecture body «uart_receiver(rtl)».

…

** Note: (vopt-143) Recognized 1 FSM in module «axi_BW_allocator(fast)».

Error loading design

[yzhou@cloud017 ~/Documents/pulpino2/sw/build]$make VERBOSE=1 helloworld.vsimc
/export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -H/export/homeO5/yzhou/Documents/pulpino2/sw -B/export/homeO5/yzhou/Documents/pulpino2/sw/build —check-build-system CMakeFiles/Makefile.cmake 0
make -f CMakeFiles/Makefile2 helloworld.vsimc
make[1]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -H/export/homeO5/yzhou/Documents/pulpino2/sw -B/export/homeO5/yzhou/Documents/pulpino2/sw/build --check-build-system CMakeFiles/Makefile.cmake 0 /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_progress_start /export/homeO5/yzhou/Documents/pulpino2/sw/build/CMakeFiles 4 make -f CMakeFiles/Makefile2 apps/helloworld/CMakeFiles/helloworld.vsimc.dir/all make[2]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make -f libs/bench_lib/CMakeFiles/bench.dir/build.make libs/bench_lib/CMakeFiles/bench.dir/depend
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends "Unix Makefiles" /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/libs/bench_lib /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/bench_lib /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/bench_lib/CMakeFiles/bench.dir/DependInfo.cmake --color= make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make -f libs/bench_lib/CMakeFiles/bench.dir/build.make libs/bench_lib/CMakeFiles/bench.dir/build
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make[3]: Nothing to be done for libs/bench_lib/CMakeFiles/bench.dir/build’.
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' [ 0%] Built target bench make -f CMakeFiles/crt0.dir/build.make CMakeFiles/crt0.dir/depend make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends «Unix Makefiles» /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/CMakeFiles/crt0.dir/DependInfo.cmake —color=
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make -f CMakeFiles/crt0.dir/build.make CMakeFiles/crt0.dir/build make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make[3]: Nothing to be done for CMakeFiles/crt0.dir/build'. make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
[ 0%] Built target crt0
make -f libs/string_lib/CMakeFiles/string.dir/build.make libs/string_lib/CMakeFiles/string.dir/depend
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends "Unix Makefiles" /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/libs/string_lib /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/string_lib /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/string_lib/CMakeFiles/string.dir/DependInfo.cmake --color= make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make -f libs/string_lib/CMakeFiles/string.dir/build.make libs/string_lib/CMakeFiles/string.dir/build
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make[3]: Nothing to be done for libs/string_lib/CMakeFiles/string.dir/build’.
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' [ 0%] Built target string make -f libs/sys_lib/CMakeFiles/sys.dir/build.make libs/sys_lib/CMakeFiles/sys.dir/depend make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends «Unix Makefiles» /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/libs/sys_lib /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/sys_lib /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/sys_lib/CMakeFiles/sys.dir/DependInfo.cmake —color=
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make -f libs/sys_lib/CMakeFiles/sys.dir/build.make libs/sys_lib/CMakeFiles/sys.dir/build make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make[3]: Nothing to be done for libs/sys_lib/CMakeFiles/sys.dir/build'. make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
[ 25%] Built target sys
make -f libs/Arduino_lib/core_libs/CMakeFiles/Arduino_core.dir/build.make libs/Arduino_lib/core_libs/CMakeFiles/Arduino_core.dir/depend
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends "Unix Makefiles" /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/libs/Arduino_lib/core_libs /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/Arduino_lib/core_libs /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/Arduino_lib/core_libs/CMakeFiles/Arduino_core.dir/DependInfo.cmake --color= make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make -f libs/Arduino_lib/core_libs/CMakeFiles/Arduino_core.dir/build.make libs/Arduino_lib/core_libs/CMakeFiles/Arduino_core.dir/build
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make[3]: Nothing to be done for libs/Arduino_lib/core_libs/CMakeFiles/Arduino_core.dir/build’.
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' [ 25%] Built target Arduino_core make -f libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/build.make libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/depend make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends «Unix Makefiles» /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/libs/Arduino_lib/separate_libs /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/Arduino_lib/separate_libs /export/homeO5/yzhou/Documents/pulpino2/sw/build/libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/DependInfo.cmake —color=
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make -f libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/build.make libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/build make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make[3]: Nothing to be done for libs/Arduino_lib/separate_libs/CMakeFiles/Arduino_separate.dir/build'. make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
[ 50%] Built target Arduino_separate
make -f apps/helloworld/CMakeFiles/helloworld.elf.dir/build.make apps/helloworld/CMakeFiles/helloworld.elf.dir/depend
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends "Unix Makefiles" /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld/CMakeFiles/helloworld.elf.dir/DependInfo.cmake --color= make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make -f apps/helloworld/CMakeFiles/helloworld.elf.dir/build.make apps/helloworld/CMakeFiles/helloworld.elf.dir/build
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make[3]: Nothing to be done for apps/helloworld/CMakeFiles/helloworld.elf.dir/build’.
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' [ 50%] Built target helloworld.elf make -f apps/helloworld/CMakeFiles/helloworld.stim.txt.dir/build.make apps/helloworld/CMakeFiles/helloworld.stim.txt.dir/depend make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends «Unix Makefiles» /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld/CMakeFiles/helloworld.stim.txt.dir/DependInfo.cmake —color=
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make -f apps/helloworld/CMakeFiles/helloworld.stim.txt.dir/build.make apps/helloworld/CMakeFiles/helloworld.stim.txt.dir/build make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
[ 50%] Generating vectors/stim.txt
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' [ 50%] Built target helloworld.stim.txt make -f apps/helloworld/CMakeFiles/helloworld.links.dir/build.make apps/helloworld/CMakeFiles/helloworld.links.dir/depend make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends «Unix Makefiles» /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld/CMakeFiles/helloworld.links.dir/DependInfo.cmake —color=
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make -f apps/helloworld/CMakeFiles/helloworld.links.dir/build.make apps/helloworld/CMakeFiles/helloworld.links.dir/build make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make[3]: Nothing to be done for apps/helloworld/CMakeFiles/helloworld.links.dir/build'. make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
[ 75%] Built target helloworld.links
make -f apps/helloworld/CMakeFiles/helloworld.slm.cmd.dir/build.make apps/helloworld/CMakeFiles/helloworld.slm.cmd.dir/depend
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends "Unix Makefiles" /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld/CMakeFiles/helloworld.slm.cmd.dir/DependInfo.cmake --color= make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make -f apps/helloworld/CMakeFiles/helloworld.slm.cmd.dir/build.make apps/helloworld/CMakeFiles/helloworld.slm.cmd.dir/build
make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make[3]: Nothing to be done for apps/helloworld/CMakeFiles/helloworld.slm.cmd.dir/build’.
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' [ 75%] Built target helloworld.slm.cmd make -f apps/helloworld/CMakeFiles/helloworld.vsimc.dir/build.make apps/helloworld/CMakeFiles/helloworld.vsimc.dir/depend make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
cd /export/homeO5/yzhou/Documents/pulpino2/sw/build && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E cmake_depends «Unix Makefiles» /export/homeO5/yzhou/Documents/pulpino2/sw /export/homeO5/yzhou/Documents/pulpino2/sw/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld/CMakeFiles/helloworld.vsimc.dir/DependInfo.cmake —color=
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make -f apps/helloworld/CMakeFiles/helloworld.vsimc.dir/build.make apps/helloworld/CMakeFiles/helloworld.vsimc.dir/build make[3]: Entering directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
[100%] Running helloworld in ModelSim
cd /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E remove stdout/*
cd /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld && /export/homeO5/yzhou/Documents/cmake/cmake-3.11.4-Linux-x86_64/bin/cmake -E remove FS/*
cd /export/homeO5/yzhou/Documents/pulpino2/sw/build/apps/helloworld && tcsh -c env VSIM_DIR=/export/homeO5/yzhou/Documents/pulpino2/vsim USE_ZERO_RISCY=0 RISCY_RV32F=0 ZERO_RV32M=0 ZERO_RV32E=0 PL_NETLIST= TB_TEST=»» /export/homeO1/mentor/questa10.4a/questasim/bin/vsim -c -64 -do ‘source tcl_files/run.tcl; run -a; exit;’ >vsim.log
Error loading design
make[3]: *** [apps/helloworld/CMakeFiles/helloworld.vsimc] Error 12
make[3]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build' make[2]: *** [apps/helloworld/CMakeFiles/helloworld.vsimc.dir/all] Error 2 make[2]: Leaving directory /export/homeO5/yzhou/Documents/pulpino2/sw/build’
make[1]: *** [apps/helloworld/CMakeFiles/helloworld.vsimc.dir/rule] Error 2
make[1]: Leaving directory `/export/homeO5/yzhou/Documents/pulpino2/sw/build’
make: *** [helloworld.vsimc] Error 2

this is the result after I added VERBOSE=1 . maybe it’s more clear

This was referenced

Dec 12, 2018

** Error: /export/homeO5/yzhou/Documents/pulpino/vsim/..//tb/tb.sv(388): Can’t have packed array of integer type.

Fix your testbench.

@quangdaovu the code I did not find packed array of integer type. what is more ,line 388 is the end of the code. I think it may be not associated to the code.

I found it!!!! at pulpino-1/tb/mem_dpi.svh,
buffer[i] = rdata_temp_arr[j][ 7:0];
buffer[i+1] = rdata_temp_arr[j][15:8];
buffer[i+2] = rdata_temp_arr[j][23:16];
buffer[i+3] = rdata_temp_arr[j][31:24];
error happened here.
The following is what I modified:
automatic logic [31:0] xxx_tmp=rdata_temp_arr[j];
buffer[i]= xxx_tmp[7:0];
buffer[i+1]=xxx_tmp[15:8];
buffer[i+2]=xxx_tmp[23:16];
buffer[i+3]=xxx_tmp[31:24];
//buffer[i] = rdata_temp_arr[j][ 7:0];
//buffer[i+1] = rdata_temp_arr[j][15:8];
//buffer[i+2] = rdata_temp_arr[j][23:16];
//buffer[i+3] = rdata_temp_arr[j][31:24];
and then,there is «helloworld» in console.But I don’t know the reason why the error happened.
If you know the reason,tell me please.Thanks!

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