Error of set pic flash addr

Topic: S9i with driver-bitmain.c:5474: Error of set PIC FLASH. (Read 589 times)

Be very careful with that HEX file. It is only supposed to be used on the T9+. See quote below from that thread:

Hello guys i had the (chain[5] PIC need restore . ) error and fixed it by using the IP Reporter Firmware restore, you can find it in Bitmain’s Forum but i leave it here for all of you

IP Reporter Restore (The miner will automatically revert to factory default firmware)

This method is only applicable to the miner as below. (The SD card slot of the miner should be on the left of Ethernet interface.

Usage: Please power off the miner, then hold down the IP Reporter and don’t release it. At the same time, please power on the miner. Releasing the IP Reporter after 5 seconds, the machine will automatically restore factory settings.

NOTE: This method is not applicable to the miner which has a SD card on the right of the Ethernet interface.

This is just a method to do a factory reset this sometimes works but not all and you are just copy pasted the guide from bitmain support without credit.
Anyway, you can find this method from here «How to reset miner to factory settings » credited to bitmain.

This is just a basic solution but if the restore factory reset doesn’t work you can try the method below.

The method to fix this issue if you have PIC error is to flashing it with PICKit 3 which is tested by some miners out there.
You can find this method from here https://bitcointalksearch.org/topic/repair-a-t9-after-a-bad-firmware-lost-chain-5032987

Hello guys i had the (chain[5] PIC need restore . ) error and fixed it by using the IP Reporter Firmware restore, you can find it in Bitmain’s Forum but i leave it here for all of you

IP Reporter Restore (The miner will automatically revert to factory default firmware)

This method is only applicable to the miner as below. (The SD card slot of the miner should be on the left of Ethernet interface.

Usage: Please power off the miner, then hold down the IP Reporter and don’t release it. At the same time, please power on the miner. Releasing the IP Reporter after 5 seconds, the machine will automatically restore factory settings.

NOTE: This method is not applicable to the miner which has a SD card on the right of the Ethernet interface.

This issue has been bugging me for some time.

I finally fixed one (by chance?) today. What I did was unplug the chain/board giving the error, flashed the same firmware through the web «Upgrade» page, let it boot, then plugged the board back in and rebooted. Full hash now.

So strange

This issue has been bugging me for some time.

I finally fixed one (by chance?) today. What I did was unplug the chain/board giving the error, flashed the same firmware through the web «Upgrade» page, let it boot, then plugged the board back in and rebooted. Full hash now.

So strange

I just started experiencing the same problem as well.

I’ve tried all of the following and still zero hashing:

1. Flashing my s9i with s9i firmware downloaded from Bitmain website
2. Flashing my s9i to latest s9 firmware
3. Flashing my s9i to older s9 firmware

Seems there is just no fix for this right now.

I have the same issue, blank hardware version and bmminer version. Also version S9i_VTest (which doesn’t seems right to me)

Does anyone have version Tue Mar 13 10:15:18 CST 2018? S9i_V2.05 This one is currently running on my other miners without a problem.

I am super slow.

As per your advice, I just got around to creating a support ticket with Bitmain, rather than proactively swapping out the control board without «permission.»

Wishing you luck on your RMA experience! I will keep my experience posted here as well!

Just shipped the S9i out to Bitmain repair facility in Washington (state). Better than having to send back to China — should be faster and definitely cheaper. Hate to loose the processing time and downtime with testing though.

Well, hopefully it comes back happy and working!

Oh, and be careful try to swap controllers if you want to try this. They made a point in submittin the repair ticket that tearing the warranty seal will void the warranty — unless Bitmain support actually told you to do so. In my case, I should be good since they told me to do it, but others on here might not be so lucky if you can’t show that their support personel told you too. You can’t swap the controllers without tearing one of their warranty tapes as they put it over one of the screws on the fan shroud plat, which has to be remove to get the controllers on/off.

Well, this did not help. I swapped an S9 controller into the S9i, re-flashed the firmware to the S9i firmware link they provided — and still the same issue!

I did also re-flash the original S9i controller with S9 firmware while in my S9 that I pulled the controller from for the S9i. It worked fine. So definitely the controller is good — well, at least it functions in the S9.

I flashed the controller in the S9i back to S9 firmware and flashed S9i firmware on the controller in the S9 and then swapped the controllers back to their original miners. This time when I flashed the S9i firmware, I did it WITHOUT keeping the previous settings to see it that would help. NOPE! Still the same issue!

Both machines booted with the improper firmware flashed to them (S9i firmware on S9 and S9 firmware on S9i). The S9 (with the S9i firmware) got similar PIC errors and would not start BMMiner — thus no mining would occur. Once the S9 had its S9 firmware back — it went back to mining just fine. But I still have a non-mining toaster for an S9i.

If this is a software fix, it would really suck to have to send it back to Bitmain in China.

Doesn’t Bitmain have a warranty place here in the US, like in California or something? I think their next step is going to be to have me to send it back.

Unless anyone else has any other ideas?

I am having the exact same issue that you describe.

driver-bitmain.c:5474: Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[5]

I thought I would try what your last post recommended, swapping an S9 control board for the S9i in question, and reflashing the firmware with the S9i firmware. . .

But how the heck do you get the control board out.

After removing all the cords, I pop the clips and begin to slide it out of the back, but it bumps into the hashing boards.

Do I have to unscrew the small control-board metal faceplate and slide it out of the front. . . ? I will research more . . .

I am following your issue since we seem to be having the same one. Have you tried this control board swap yet? Did it work?

They gave directions and a link to a YouTube video showing the process. Here is their response telling me what to do here:

You could use the S9 controller but be sure to reflash the S9i firmware https://shop.bitmain.com/support.htm?pid=00720180525135351672WCe9WPkv06BF

How to disassemble and reassemble S9/T9 control boards:
1. Unplug the fans and flat cable. Please handle the clip-on plug carefully.
2. Remove the four mounting screws of the fan shroud and put aside the fan. Keep the screws in a safe place.
3. Remove the control board from the card slot.
4. Push aside the two leaf springs and remove the control board.
5. To install the control board reverse the above steps.

Please let us know if you have additional questions or concerns.

If you get this done before me please post your results. I may get to it tonight, but maybe not until as late as Sunday evening.

I am having the exact same issue that you describe.

driver-bitmain.c:5474: Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[5]

I thought I would try what your last post recommended, swapping an S9 control board for the S9i in question, and reflashing the firmware with the S9i firmware. . .

But how the heck do you get the control board out.

After removing all the cords, I pop the clips and begin to slide it out of the back, but it bumps into the hashing boards.

Do I have to unscrew the small control-board metal faceplate and slide it out of the front. . . ? I will research more . . .

I am following your issue since we seem to be having the same one. Have you tried this control board swap yet? Did it work?

First off, the bitmain response is essentially worthless boilerplate and unrelated to your problem, so you can ignore it.

Basically, the S9i firmware and the newer S9 firmware will hang and stop booting when this error is encountered. On the S9, you can work around this issue by installing a previous version of the firmware. Unfortunately, that doesn’t help you since you need S9i firmware. Perhaps bitmain warranty rma is your only option, although there must be some fix for this that I’m not aware of.

More or less — that’s what I thought. I have gotten another message from them after I updated them with answers to their test list. Now they want me to take an S9 controller board and swap it out with the controller board on this S9i — then re-flash it with the S9i firmware from their site. If that works, then they will send me a replacement controller. Does that make sense? I don’t know what these PIC things are — so not sure if this is a viable solution/test. If the PICs are on the controller, then I suppose this would make sense and this test would verify if there’s some kind of controller flaw.

Not sure why going to an older version of the firmware with the S9’s would solve this — unless the newer firmware is trying to do something particular with the controller that the older firmware is not. Maybe for efficiency purposes? Maybe this could truly indicate a problem with the controller that simply isn’t noticed with an older firmware. Anyway, now I have to go through this process to see if it helps. If the S9 controller works — I wonder if I couldn’t re-flash the S9i controller with the S9 firmware and literally just swap the controllers. Maybe use an earlier version of the S9 firmware if it shows the same issue. If that works then could have them up faster while they have a controller on the way.

Источник

Hello there, I have recently bought a Antminer t9, and I am having some problems, the board says :

Hardware Version Socket connect failed: Connection refused.

I have :

1. rebooted

2. Let it run for more than one hour ( And the button at the front where it says normal ) starts glowing green, but my miner is not mining.

I have to say that when i first plugged it in, it was working, but when I chagned the address to nice hash while it said no hashing detected on the board apprently nicehash got something for couple of minutes )

Now my problem is I am kinda stuck what to do.

oh and Kernel Log keeps saying :

Check chain[1] PIC fw version=0x00 chain[1] PIC need restore … Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] After restore: chain[1] PIC fw version=0x00 chain[1] PIC need restore … Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[1] After restore: chain[1] PIC fw version=0x00 Check chain[2] PIC fw version=0x00 chain[2] PIC need restore … Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] After restore: chain[2] PIC fw version=0x00 chain[2] PIC need restore … Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2] Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[2]

Anybody had similar issues ,and fix

Thank you for your time

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[ 1.945966] ALSA device list:
[ 1.945970] No soundcards found.
[ 1.962393] UBIFS: background thread «ubifs_bgt0_0» started, PID 1082
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[ 2.139164] devtmpfs: mounted
[ 2.142268] Freeing unused kernel memory: 204K (c06d2000 — c0705000)
[ 2.942750] random: dd urandom read with 0 bits of entropy available
[ 3.186635]
[ 3.186635] bcm54xx_config_init
[ 3.786626]
[ 3.786626] bcm54xx_config_init
[ 6.787458] xemacps e000b000.ps7-ethernet: Set clk to 24999999 Hz
[ 6.793549] xemacps e000b000.ps7-ethernet: link up (100/FULL)
[ 19.845992] In axi fpga driver!
[ 19.849085] request_mem_region OK!
[ 19.852456] AXI fpga dev virtual address is 0xf01fe000
[ 19.857583] *base_vir_addr = 0xfc510
[ 19.867404] In fpga mem driver!
[ 19.872736] request_mem_region OK!
[ 19.876340] fpga mem virtual address is 0xf3000000
[ 20.896034]
[ 20.896034] bcm54xx_config_init
[ 22.125936]
[ 22.125936] bcm54xx_config_init
[ 25.126417] xemacps e000b000.ps7-ethernet: Set clk to 24999999 Hz
[ 25.132431] xemacps e000b000.ps7-ethernet: link up (100/FULL)
[ 158.713714] random: nonblocking pool is initialized
Detect 1GB control board of XILINX
Miner Type = S9
Miner compile time: Wed Jun 10 11:48:25 CST 2020 type: Antminer S9 (vnish 3.8.6)
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x00000000
set_reset_allhashboard = 0x0000ffff
set_reset_allhashboard = 0x0000ffff
Checking fans!
1 fan ok
2 fan ok
set_reset_allhashboard = 0x0000ffff
Error of set PIC FLASH addr: addr_H=f(0) addr_L=e8(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=f(0) addr_L=e8(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=f(0) addr_L=e8(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=f(0) addr_L=e8(0) on Chain[0]
Check chain[0] PIC fw version=0x00
chain[0] PIC need restore …
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
After restore: chain[0] PIC fw version=0x00
chain[0] PIC need restore …
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[0]
After restore: chain[0] PIC fw version=0x00
Error of set PIC FLASH addr: addr_H=f(0) addr_L=e8(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=f(0) addr_L=e8(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=f(0) addr_L=e8(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=f(0) addr_L=e8(0) on Chain[4]
Check chain[4] PIC fw version=0x00
chain[4] PIC need restore …
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[4]
Error of set PIC FLASH addr: addr_H=3(0) addr_L=0(0) on Chain[4]

1.

Issue: The miner has no hash rate. One of the hash board’s temperature exceeds 80 degree Celsius.

Reason: A piece of heat sink is loose or dropped off.

Solution: Remove the hash board that exceeds 80 degree Celsius to repair.

Note: If large quantity of hash boards temperature exceeds 80 degree Celsius, please add cooling devices, as the high temperature will ultimately go into the high temperature protection mode and the miner will shut down. Moreover, the miner can easily get defective when working in a high temperature environment.

2.

Issue: The hash rate is good, but there is no temperature shown on the Miner status.

The hash board is easily burnt if there is no temperature shown for monitoring or when the real temperature is very high

Reason: The temperature detector is damaged on one of the hash boards that lead to the other two hash boards to have the issues on temperature display as well.

Solution: Test the 3 hash boards one by one by connecting to the control board and let it run for about 5 minutes, find the faulty hash board with temperature detection problem and ship it back to repair.

3.

Issue: The hash rate is lower than normal. There is an “X” shown on the Miner status.

Reason: The ASIC chip is damaged, which resulted in the loss of some hash rate on the hash board.

Solution: If that hash board can still work well, you can keep and continue to let it work. There is no need to repair it unless the hash board becomes totally defective.

4.

Issue: The hash rate is lower than normal. There are a lot of “X” shown on Miner status

Reason: The chips are damaged, which lead to the entire hash board running abnormally.

Solution: Remove the hash board to repair.

5.

Issue: The hash rate is lower than normal. There are a lot of “-” shown on Miner status

Reason: It may be caused by instability of the PSU voltage or a defective hash board.

Solution: Replace the PSU and control board-hash board 18 pin ribbon cable. If replacing didn’t work, please remove the hash board to repair.

6.

Issue: The hash rate is lower than normal. Some chips are lost. The hash rate is only running at 2/3 of the normal.

Reason: Chain scission of chips

Solution: Remove the hash board to repair.

7.

Issue: The miner has no hash rate. There is X.X.X.X shown on the Hardware Version. Hash board cannot be detected. There is no information shown at all on the Miner status interface.

Cause: The firmware of miner is not detected.

Solution: Power off the miner and reset it. Reload the firmware.

8.

Issue: The miner worked great when it was powered. After awhile, there is no hash rate.

Reason: One of the fans is not detected. Miner will work well only when both fans are detected.

Solution: Switch the control board connection between the two fans to find out which one is defective.

9.

Issue: A large number of Antpools surfaced. Hash rate is normal. There is no use resetting the router.

Reason: One of the computers in the network has been infected by virus or malware.

Solution: Find infected computer and remove the virus or malware.

10.

Issue: Miner can’t find IP. Red light flashing; Green light does not blink

— Reason：The Miner is not connected with the Internet.

Solution: Test the Internet cable, connection and the settings of the Internet (DHCP mode is required).

— Reason: The miner program has not started.

Solution: Reset the miner several times.

— Reason: The application of miner is lost.

Solution: Perform control board recovery

11.

Issue: The miner doesn’t work after powering on despite changing the PSU.

— Reason: There is a short circuit inside one of the hash boards.

Solution: Find which hash board is defective. Remove the defective part to repair.

— Reason: Control board failure

Solution: Change the control board

12.

Issue: PSU can’t work when if the PSU fan is running. Miner works well after changing PSU.

Reason: The PSU is defective. The PSU fan is powered by a different output. The defect can’t be judged by whether the fan rotation power is normal.

Solution: Ship back the PSU to repair.

13.

Issue: Miner restores to factory setting after powering off.

Reason：The software in BB board is damaged.

Solution: Perform control board recovery

14.

Issue: Miners work well for several month before it starts to malfunction.

— Reason: The hash boards were corroded by humidity and lots of dust.

Solution: Remove the defective hash boards, dust the miner and reduce air humidity.

— Reason: Large amount of dust, resulting in congestion in the air duct. Heat can’t be dissipated. Catkins are likely to cause congestion in air duct.

Solution: Remove the defective hash boards, dust the miner and add dust elimination.

15.

Issue: The machine is defective when network changed

Reason: Due to the network setup, miner can’t find the IP.

Solution: Power off and reset the miner.

Issue: S7 malfunction after running for a while. It runs again after rebooting.

-Reason: Temperature exceeds 80 degree Celsius and miner will automatically shut down.

Solution: Increase the amount of air flow.

— Reason: The PGA in BB board weld badly, which lead to miner’s shut down.

Solution: Remove the BB board to repair.

17.

Issue: PSU can’t work but fan is running. All the indicators are off.

Reason: The control board cannot get power as the power circuit in IO board is damaged.

Solution: Switch the BB Board and IO Board with good miner to troubleshoot the defective parts.

how this my issue

Hi, mi new S9 it doesnt works with the 3 has board, i can see one of them in the miner status. What can i do?

Hi, my S9 after working a few weeks is only detecting 2 hashboards. I tried switching the hashboard to a good miner and wasn’t detected either. Also switched a good hashboard to the bad miner, and was working Ok. I believe the hashboard is broken, I can’t get it detected in any of my miners. Should I send it to repair?

If you have not already done so please email us at support@bitmain.com. We can help you with your specific issue.

I’m having trouble with Issue #7. I get the hardware version x.x.x.x and no «miner status» information. however, when i run a reset, the information is shown for a while, about 01 minute then it goes blank again. The information shown with the default settings is between normal, no x’s found on ACIS Status, and Temperature around 50ºC.

I’ve been looking for a firmware update, but i’m not sure wich one to install. Curious thing, I own 02 Antminers S7, and both came up with the same issue at the same time. so i do not think it is related to hardware problems

Any information you can provide will be very helpful

Hi Rafael. Thank you for submitting a ticket. I have responded to the ticket with the information that you requested.

Hi, i have an S9, and one of the boards showme a lots of «x», then i restart my miner, from the control panel, now the board doesnt turn on. Only two of the 3 boards turns on the red led in the board, and the damaged card does’nt start, load or turn on. I need to remove the damaged board to send it bitmain. Please help.

I have my s7 cards have been damaging, sometimes when the frequency of 700 to 600 step back on sometimes not and in one of the cases the card comes on but the s7 does not have the same power does not reach 4.73

note:in this example the machine had only on card put it at 600 and set the 3 then appeared 3 lit and at the time under the speed restart it and put it in 700 and was thus

note: in this case the only way to start the first card was to put the frequency in 600 and yet not hashea at the speed that should

so I have several cases as well and need to find a solution because you will understand I made an investment and thus won’t be able to recover it

All 17 of my miners stopped working at the same time and now say «socket connection failed. » Please help!

Good morning, I request your help since my S9 has presented a problem.

The temperature of the third hashboard is no longer displayed and two groups of zeros have disappeared in the ASIC state. This has caused the hash rate to be less than normal, obviously the hashboard does not work properly.

Reset the S9 and the values will not be reactivated.

What can I do to resolve this situation? What is happening?

I am able to get a IP address on my L3+ But I am unable to connect via the PC to the Backdoor portal . Air in fan spins at startup the exhaustr fans spins toward the end of the boot process at high speed only. the inter net lights flash green then they go out then come back and then I get a Blinking red light and it turns into a solid red light. PLEASE PLEASE Help Me. Most gracious.

Hi, please submit a support ticket so that we can help you troubleshoot. You can submit the ticket right from our web site.

I have a problem. Chain # 6 is not shown in the tabs «Miner status».
Chain # 7 does not show the temperature of chip 1 and chip 2.
GH / s (rt) — 10995.

I turn on the s9, the red led light on the chain # 6

.

What should I order for repair? I still have a guarantee.

Same issue for me #6. One of my hashing boards does not show up or work anymore. It seems many of us with S9’s are having this problem right now. I’m so upset. I put so much into this. What do I do now? Can’t you just send me a replacement hash board asap please?

I am seeing multiple people this month with the same problem as me, One hashing board and temps and zero’s no longer show up or works anymore. Has this problem been addressed for anyone?

Hi Edward, please submit a support ticket so that we can help you troubleshoot. Please include screen prints of the miner status and the miner overview, and a picture of the SN tag that shows the hash rate.

Yes I have submitted support tickets and I just added screenshots in the reply section of the support e mail. Can you confirm you have received it? I’m so stressed out over this right now been up all night. Please advise. Thank you.

Edward, hi.
They will not send you a new card (panel), I was told to ship the device entirely to China. You are lucky, there is a service center in the USA, but in Russia there is not. I asked to send me a fee, I will install it myself. Have refused. I can not send, one of my devices was lost and three months I can not find out what’s wrong with my device.

This is horrible news. It seems like if the other two boards are working fine then sending a replacement board would be the best option. I am still under warranty but I really do not want to send the whole machine back and pay shipping in addition to losing the mining profits and risk more damage or the miner getting lost in the mail. This sucks. I talked bitmain up a lot and referred a lot of friends and now I am really worried. I was told by support when I ordered that these machines should last for years. I’ve taken great care of it and spent all this time and money for a costly return and headache? So bummed out right now. I don’t even want the 2 L3+ I ordered. What’s the point if they break so soon and repair is so hard? Wishing I never decided to mine right now guess everyone was right.

Hi Edward, I just sent you instructions to first try resetting the miner. That sometimes fixes the issue and avoids the need to ship the machine for repair.

I tried resetting and loading the firmware you sent me and it is still the same problem. One hash board has completely disappeared from my mining status screen and is 1/3 less the hashing power. I emailed you all the screenshots you requested as well, Please help me thank you.

I really hope bitmain can do right by me for this. I have been a loyal customer. I have placed several other orders with you and spread a lot of good word about you on facebook and referred many friends. Please help me out on this I have placed much faith in you and am very nervous right now about my S9 I’ve only had it a few months.

I have new batch of L3+ and 1 of the units hashboard is not working. please send new board.

I am so upset. I have been patient and followed every step of your repair process with my S9 which is still under warranty. I created a support ticket, troubleshooted with support, was instructed to pay shipping and ship the whole miner to California for repair, which I did. I received an e mail saying repair or replacement of my broken hash board was complete and I would have my S9 back in full working condition in 3 days. I was very impressed by support and the warranty process at this point even though I had spent so much time on this and paid for shipping. Received mu miner yesterday and it is in the same exact condition. It still does NOT work and the same hash board is still broken and my S9 still only hashes at 2/3 of it’s hashing power. Why? Why would you put me through all this work and have me pay shipping and just send back the miner to me in the exact same condition? Why? I have been so polite. I have followed all your repair instructions and I am still under warranty. Why are you putting me through so much grief? I don’t understand and feel like just giving up on mining all together.

nicson1989

Свой человек

pyhtin79

Пляшущий с бубном

lasthiter

Свой человек

Попробуй сделать вот это, у меня тоже самое было, те же 400, пока я не проделал такую манипуляцию.

Включение параметра «Блокировка страниц в памяти»

В меню Пуск выберите команду Выполнить. В окне Открыть введите gpedit.msc.

В консоли Редактор локальных групповых политик разверните узел Конфигурация компьютера, затем узел Конфигурация Windows.

Разверните узлы Настройки безопасностии Локальные политики.

Выберите папку Назначение прав пользователя .

Политики будут показаны на панели подробностей.

На этой панели дважды щелкните параметр Блокировка страниц в памяти.

В диалоговом окне Параметр локальной безопасности — блокировка страниц в памяти щелкните Добавить пользователя или группу.

В диалоговом окне Выбор: пользователи, учетные записи служб или группы добавьте учетную запись, обладающую правами доступа для запуска sqlservr.exe.

Чтобы изменения вступили в силу, выйдите из системы и снова войдите.

iDekabrist

Бывалый

pyhtin79

Пляшущий с бубном

Попробуй сделать вот это, у меня тоже самое было, те же 400, пока я не проделал такую манипуляцию.

Включение параметра «Блокировка страниц в памяти»

В меню Пуск выберите команду Выполнить. В окне Открыть введите gpedit.msc.

В консоли Редактор локальных групповых политик разверните узел Конфигурация компьютера, затем узел Конфигурация Windows.

Разверните узлы Настройки безопасностии Локальные политики.

Выберите папку Назначение прав пользователя .

Политики будут показаны на панели подробностей.

На этой панели дважды щелкните параметр Блокировка страниц в памяти.

В диалоговом окне Параметр локальной безопасности — блокировка страниц в памяти щелкните Добавить пользователя или группу.

В диалоговом окне Выбор: пользователи, учетные записи служб или группы добавьте учетную запись, обладающую правами доступа для запуска sqlservr.exe.

Чтобы изменения вступили в силу, выйдите из системы и снова войдите.

/* * Copyright 2016-2017 Fazio Bai <yang.bai@bitmain.com> * Copyright 2016-2017 Clement Duan <kai.duan@bitmain.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the Free * Software Foundation; either version 3 of the License, or (at your option) * any later version. See COPYING for more details. */ #ifndef C5_H #define C5_H //FPGA rgister Address Map #define HARDWARE_VERSION (0x00000000/sizeof(int)) #define FAN_SPEED (0x00000004/sizeof(int)) #define HASH_ON_PLUG (0x00000008/sizeof(int)) #define BUFFER_SPACE (0x0000000c/sizeof(int)) #define RETURN_NONCE (0x00000010/sizeof(int)) #define NONCE_NUMBER_IN_FIFO (0x00000018/sizeof(int)) #define NONCE_FIFO_INTERRUPT (0x0000001c/sizeof(int)) #define TEMPERATURE_0_3 (0x00000020/sizeof(int)) #define TEMPERATURE_4_7 (0x00000024/sizeof(int)) #define TEMPERATURE_8_11 (0x00000028/sizeof(int)) #define TEMPERATURE_12_15 (0x0000002c/sizeof(int)) #define IIC_COMMAND (0x00000030/sizeof(int)) #define RESET_HASHBOARD_COMMAND (0x00000034/sizeof(int)) #define BMC_CMD_COUNTER (0x00000038/sizeof(int)) #define TW_WRITE_COMMAND (0x00000040/sizeof(int)) #define QN_WRITE_DATA_COMMAND (0x00000080/sizeof(int)) #define FAN_CONTROL (0x00000084/sizeof(int)) #define TIME_OUT_CONTROL (0x00000088/sizeof(int)) #define TICKET_MASK_FPGA (0x0000008c/sizeof(int)) #define HASH_COUNTING_NUMBER_FPGA (0x00000090/sizeof(int)) #define SNO (0x00000094/sizeof(int)) #define BC_WRITE_COMMAND (0x000000c0/sizeof(int)) #define BC_COMMAND_BUFFER (0x000000c4/sizeof(int)) #define FPGA_CHIP_ID_ADDR (0x000000f0/sizeof(int)) #define CRC_ERROR_CNT_ADDR (0x000000f8/sizeof(int)) #define DHASH_ACC_CONTROL (0x00000100/sizeof(int)) #define COINBASE_AND_NONCE2_LENGTH (0x00000104/sizeof(int)) #define WORK_NONCE_2 (0x00000108/sizeof(int)) #define NONCE2_AND_JOBID_STORE_ADDRESS (0x00000110/sizeof(int)) #define MERKLE_BIN_NUMBER (0x00000114/sizeof(int)) #define JOB_START_ADDRESS (0x00000118/sizeof(int)) #define JOB_LENGTH (0x0000011c/sizeof(int)) #define JOB_DATA_READY (0x00000120/sizeof(int)) #define JOB_ID (0x00000124/sizeof(int)) #define BLOCK_HEADER_VERSION (0x00000130/sizeof(int)) #define TIME_STAMP (0x00000134/sizeof(int)) #define TARGET_BITS (0x00000138/sizeof(int)) #define PRE_HEADER_HASH (0x00000140/sizeof(int)) //FPGA registers bit map //QN_WRITE_DATA_COMMAND #define RESET_HASH_BOARD (1 << 31) #define RESET_ALL (1 << 23) #define CHAIN_ID(id) (id << 16) #define RESET_FPGA (1 << 15) #define RESET_TIME(time) (time << 0) #define TIME_OUT_VALID (1 << 31) //RETURN_NONCE #define WORK_ID_OR_CRC (1 << 31) #define WORK_ID_OR_CRC_VALUE(value) ((value >> 16) & 0x7fff) #define NONCE_INDICATOR (1 << 7) #define CHAIN_NUMBER(value) (value & 0xf) #define REGISTER_DATA_CRC(value) ((value >> 24) & 0x7f) //BC_WRITE_COMMAND #define BC_COMMAND_BUFFER_READY (1 << 31) #define BC_COMMAND_EN_CHAIN_ID (1 << 23) #define BC_COMMAND_EN_NULL_WORK (1 << 22) //NONCE2_AND_JOBID_STORE_ADDRESS #define JOB_ID_OFFSET (0x0/sizeof(int)) #define HEADER_VERSION_OFFSET (0x4/sizeof(int)) #define NONCE2_L_OFFSET (0x8/sizeof(int)) #define NONCE2_H_OFFSET (0xc/sizeof(int)) #define MIDSTATE_OFFSET 0x20 //DHASH_ACC_CONTROL #define VIL_MODE (1 << 15) #define VIL_MIDSTATE_NUMBER(value) ((value & 0x0f) << 8) #define NEW_BLOCK (1 << 7) #define RUN_BIT (1 << 6) #define OPERATION_MODE (1 << 5) //NONCE_FIFO_INTERRUPT #define FLUSH_NONCE3_FIFO (1 << 16) //ASIC macro define //ASIC register address #define C5_VERSION 1 #define CHIP_ADDRESS 0x0 #define GOLDEN_NONCE_COUNTER 0x8 #define PLL_PARAMETER 0xc #define START_NONCE_OFFSET 0x10 #define HASH_COUNTING_NUMBER 0x14 #define TICKET_MASK 0x18 #define MISC_CONTROL 0x1c #define GENERAL_I2C_COMMAND 0X20 //ASIC command #define SET_ADDRESS 0x1 #define SET_PLL_DIVIDER2 0x2 #define PATTERN_CONTROL 0x3 #define GET_STATUS 0x4 #define CHAIN_INACTIVE 0x5 #define SET_BAUD_OPS 0x6 #define SET_PLL_DIVIDER1 0x7 #define SET_CONFIG 0x8 #define COMMAND_FOR_ALL 0x80 //other ASIC macro define #define MAX_BAUD_DIVIDER 26 #define DEFAULT_BAUD_DIVIDER 26 #define VIL_COMMAND_TYPE (0x02 << 5) #define VIL_ALL (0x01 << 4) #define PAT (0x01 << 7) #define GRAY (0x01 << 6) #define INV_CLKO (0x01 << 5) #define LPD (0x01 << 4) #define GATEBCLK (0x01 << 7) #define RFS (0x01 << 6) #define MMEN (0x01 << 7) #define TFS(x) ((x & 0x03) << 5) // Pic #define PIC_FLASH_POINTER_START_ADDRESS_H 0x03 #define PIC_FLASH_POINTER_START_ADDRESS_L 0x00 #define PIC_FLASH_POINTER_END_ADDRESS_H 0x0f #define PIC_FLASH_POINTER_END_ADDRESS_L 0x7f #define PIC_FLASH_LENGTH (((unsigned int)PIC_FLASH_POINTER_END_ADDRESS_H<<8 + PIC_FLASH_POINTER_END_ADDRESS_L) — ((unsigned int)PIC_FLASH_POINTER_START_ADDRESS_H<<8 + PIC_FLASH_POINTER_START_ADDRESS_L) + 1) #define PIC_FLASH_SECTOR_LENGTH 32 #define PIC_SOFTWARE_VERSION_LENGTH 1 #define PIC_VOLTAGE_TIME_LENGTH 6 #define PIC_COMMAND_1 0x55 #define PIC_COMMAND_2 0xaa #define SET_PIC_FLASH_POINTER 0x01 #define SEND_DATA_TO_IIC 0x02 // just send data into pic’s cache #define READ_DATA_FROM_IIC 0x03 #define ERASE_IIC_FLASH 0x04 // erase 32 bytes one time #define WRITE_DATA_INTO_PIC 0x05 // tell pic write data into flash from cache #define JUMP_FROM_LOADER_TO_APP 0x06 #define RESET_PIC 0x07 #define GET_PIC_FLASH_POINTER 0x08 #define ERASE_PIC_APP_PROGRAM 0x09 #define SET_VOLTAGE 0x10 #define SET_VOLTAGE_TIME 0x11 #define SET_HASH_BOARD_ID 0x12 #define GET_HASH_BOARD_ID 0x13 #define SET_HOST_MAC_ADDRESS 0x14 #define ENABLE_VOLTAGE 0x15 #define SEND_HEART_BEAT 0x16 #define GET_PIC_SOFTWARE_VERSION 0x17 #define GET_VOLTAGE 0x18 #define GET_DATE 0x19 #define GET_WHICH_MAC 0x20 #define GET_MAC 0x21 #define WR_TEMP_OFFSET_VALUE 0x22 #define RD_TEMP_OFFSET_VALUE 0x23 //diff freq #define PIC_FLASH_POINTER_FREQ_START_ADDRESS_H 0x0F #define PIC_FLASH_POINTER_FREQ_START_ADDRESS_L 0xA0 #define PIC_FLASH_POINTER_FREQ_END_ADDRESS_H 0x0f #define PIC_FLASH_POINTER_FREQ_END_ADDRESS_L 0xDF #define FREQ_MAGIC 0x7D // BAD CORE NUM #define PIC_FLASH_POINTER_BADCORE_START_ADDRESS_H 0x0F #define PIC_FLASH_POINTER_BADCORE_START_ADDRESS_L 0x80 #define PIC_FLASH_POINTER_BADCORE_END_ADDRESS_H 0x0f #define PIC_FLASH_POINTER_BADCORE_END_ADDRESS_L 0x9F #define BADCORE_MAGIC 0x23 // magic number for bad core num #define HEART_BEAT_TIME_GAP 10 // 10s #define IIC_READ (1 << 25) #define IIC_WRITE (~IIC_READ) #define IIC_REG_ADDR_VALID (1 << 24) //#define IIC_ADDR_HIGH_4_BIT (0x0A << 20) #define IIC_CHAIN_NUMBER(x) ((x & 0x0f) << 16) #define IIC_REG_ADDR(x) ((x & 0xff) << 8) // AT24C02 #define AT24C02_ADDRESS 0x50 #define EEPROM_LENGTH 256 #define HASH_ID_ADDR 0x80 #define VOLTAGE_ADDR 0x90 #define SENSOR_OFFSET_ADDR 0x98 #define VOLTAGE_SET_TIME 0xA0 #define VOLTAGE_SET_TIME 0xA0 #define FREQ_BADCORE_ADDR 0x00 // 128 bytes 0 — 0x7F //other FPGA macro define #define TOTAL_LEN 0x160 #define FPGA_MEM_TOTAL_LEN (16*1024*1024) // 16M bytes #define HARDWARE_VERSION_VALUE 0xC501 #define NONCE2_AND_JOBID_STORE_SPACE (2*1024*1024) // 2M bytes #define NONCE2_AND_JOBID_STORE_SPACE_ORDER 9 // for 2M bytes space #define JOB_STORE_SPACE (1 << 16) // for 64K bytes space #define JOB_START_SPACE (1024*8) // 8K bytes #define JOB_START_ADDRESS_ALIGN 32 // JOB_START_ADDRESS need 32 bytes aligned #define NONCE2_AND_JOBID_ALIGN 64 // NONCE2_AND_JOBID_STORE_SPACE need 64 bytes aligned #define MAX_TIMEOUT_VALUE 0x1ffff // defined in TIME_OUT_CONTROL #define MAX_NONCE_NUMBER_IN_FIFO 0x1ff // 511 nonce #define NONCE_DATA_LENGTH 4 // 4 bytes #define REGISTER_DATA_LENGTH 4 // 4 bytes #define TW_WRITE_COMMAND_LEN 52 #define TW_WRITE_COMMAND_LEN_VIL 52 #define NEW_BLOCK_MARKER 0x11 #define NORMAL_BLOCK_MARKER 0x01 // ATTENTION: if MEM size is changed, must change this micro definition too!!! use MAX size (BYTE) — 16 MB as FPGA start memory address #define PHY_MEM_NONCE2_JOBID_ADDRESS_XILINX_1GB ((1024—16)*1024*1024) #define PHY_MEM_NONCE2_JOBID_ADDRESS_XILINX_512MB ((512—16)*1024*1024) // XILINX use 512MB memory #define PHY_MEM_NONCE2_JOBID_ADDRESS_XILINX_256MB ((256—16)*1024*1024) // XILINX use 512MB memory #define PHY_MEM_NONCE2_JOBID_ADDRESS_C5 ((1024—16)*1024*1024) extern unsigned int PHY_MEM_NONCE2_JOBID_ADDRESS; #define PHY_MEM_JOB_START_ADDRESS_1 (PHY_MEM_NONCE2_JOBID_ADDRESS + NONCE2_AND_JOBID_STORE_SPACE) #define PHY_MEM_JOB_START_ADDRESS_2 (PHY_MEM_JOB_START_ADDRESS_1 + JOB_STORE_SPACE) #include «miner_type.h« // use setminertype to define miner type in this file instead of belows!!! //#define R4 // if defined , for R4 63 chips //#define S9_PLUS // if defined , for T9 57 chips //#define S9_63 // if defined , for S9 63 chips //#define T9_18 // if defined , for T9+ 18 chips #define RESET_KEEP_TIME 3 // keep reset signal for 1 secnods #undef USE_OPENCORE_ONEBYONE // if defined, we will use open core one by one, do 114 times on open core for each chain! but NOT WORKS!?? #define ENABLE_PREHEAT #undef ENABLE_REGISTER_CRC_CHECK //if defined, will drop the register buffer with crc error! #define REBOOT_TEST_ONCE_1HOUR //if defined, will check hashrate after 1 hour, and reboot only once #define ENABLE_FINAL_TEST_WITHOUT_REBOOT // when REBOOT_TEST_ONCE_1HOUR enabeld and this defined, the miner will not reboot after test for 1 hours, then we can save time. test system will treat these miners as good with green color. #define DISABLE_FINAL_TEST //if defined, it will set rebootTestNum=0 and restartNum=2 to indicate the the miner fw is in normal user mode , not test mode #define DISABLE_SHOWX_ENABLE_XTIMES // if defined, will disable x show on web UI, but will enable x times counter in 1 mins #define FASTER_TESTPATTEN // will use 9% timeout to test patten #undef USE_OPENCORE_TWICE #undef ENABLE_REINIT_WHEN_TESTFAILED #define RESET_HASHBOARD_TIME 15 #define ENABLE_CHECK_PIC_FLASH_ADDR // if enabled, will check PIC FLASH ADDR value , set and read back to compare from PIC #define ENABLE_RESTORE_PIC_APP // if enabled, will restore PIC APP when the version is not correct!!! #ifdef R4 #define USE_N_OFFSET_FIX_TEMP // if defined, we will use n and offset to fix temp value #define EXTEND_TEMP_MODE // if defined, we set temp value area from -64 to 191 as extended temp #define ENABLE_HIGH_VOLTAGE_OPENCORE #define PIC_VERSION 0x03 #define CHAIN_ASIC_NUM 63 #define R4_MAX_VOLTAGE_C5 890 #define R4_MAX_VOLTAGE_XILINX 910 #define FIX_BAUD_VALUE 1 #define UPRATE_PERCENT 1 // means we need reserved more 1% rate #define HIGHEST_VOLTAGE_LIMITED_HW 940 //measn the largest voltage, hw can support #define USE_NEW_RESET_FPGA #undef USE_PREINIT_OPENCORE // if defined, we will open core at first ,then get asicnum and do other init process #endif #ifdef S9_PLUS #define ENABLE_HIGH_VOLTAGE_OPENCORE #define S9_PLUS_VOLTAGE2 //if defined, then it support S9+ new board with new voltage controller #define PIC_VERSION 0x03 #define CHAIN_ASIC_NUM 57 #define USE_N_OFFSET_FIX_TEMP // if defined, we will use n and offset to fix temp value #define EXTEND_TEMP_MODE // if defined, we set temp value area from -64 to 191 as extended temp #define HIGHEST_VOLTAGE_LIMITED_HW 970 //measn the largest voltage, hw can support #define FIX_BAUD_VALUE 1 #define UPRATE_PERCENT 2 // means we need reserved more 2% rate #define USE_NEW_RESET_FPGA #undef USE_PREINIT_OPENCORE // if defined, we will open core at first ,then get asicnum and do other init process #endif #ifdef S9_63 #define ENABLE_HIGH_VOLTAGE_OPENCORE #define PIC_VERSION 0x03 #define CHAIN_ASIC_NUM 63 #define USE_N_OFFSET_FIX_TEMP // if defined, we will use n and offset to fix temp value #define EXTEND_TEMP_MODE // if defined, we set temp value area from -64 to 191 as extended temp #define FIX_BAUD_VALUE 1 #define UPRATE_PERCENT 1 // means we need reserved more 1% rate #define HIGHEST_VOLTAGE_LIMITED_HW 940 //measn the largest voltage, hw can support #define USE_NEW_RESET_FPGA #undef USE_PREINIT_OPENCORE // if defined, we will open core at first ,then get asicnum and do other init process #endif #ifdef T9_18 #define ENABLE_HIGH_VOLTAGE_OPENCORE // T9+ use this , will cause error on chips, because the voltage changing need a long time to balance #define PIC_VERSION 0x03 #define CHAIN_ASIC_NUM 18 #define USE_N_OFFSET_FIX_TEMP // if defined, we will use n and offset to fix temp value #define EXTEND_TEMP_MODE // if defined, we set temp value area from -64 to 191 as extended temp #define FIX_BAUD_VALUE 1 #define UPRATE_PERCENT 2 // means we need reserved more 2% rate #define HIGHEST_VOLTAGE_LIMITED_HW 930 //measn the largest voltage, hw can support #define USE_NEW_RESET_FPGA #undef USE_PREINIT_OPENCORE // if defined, we will open core at first ,then get asicnum and do other init process #endif #ifdef USE_PREINIT_OPENCORE #define ENABLE_SET_TICKETMASK_BEFORE_TESTPATTEN // a bug, do not know reason: asic ticket mask > 0 even after reset asic!!! #else #undef ENABLE_SET_TICKETMASK_BEFORE_TESTPATTEN // a bug, do not know reason: asic ticket mask > 0 even after reset asic!!! #endif #define ASIC_TYPE 1387 // 1385 or 1387 #define CHIP_ADDR_INTERVAL 4 // fix chip address interval = 4 #define DEFAULT_BAUD_VALUE 26 #define ASIC_CORE_NUM 114 #define BM1387_CORE_NUM ASIC_CORE_NUM // macro define about miner #define BITMAIN_MAX_CHAIN_NUM 16 #define BITMAIN_MAX_FAN_NUM 8 // FPGA just can supports 8 fan #define BITMAIN_DEFAULT_ASIC_NUM 64 // max support 64 ASIC on 1 HASH board #define MIDSTATE_LEN 32 #define DATA2_LEN 12 #define MAX_RETURNED_NONCE_NUM 10 #define PREV_HASH_LEN 32 #define MERKLE_BIN_LEN 32 #define INIT_CONFIG_TYPE 0x51 #define STATUS_DATA_TYPE 0xa1 #define SEND_JOB_TYPE 0x52 #define READ_JOB_TYPE 0xa2 #define CHECK_SYSTEM_TIME_GAP 10000 // 10s //fan // BELOW IS ALL FOR DEBUG !!! normally all must be undefined!!! #undef DEBUG_KEEP_USE_PIC_VOLTAGE_WITHOUT_CHECKING_VOLTAGE_OF_SEARCHFREQ // if defined, will read pic voltage at first , and use this voltage in mining as working voltage, ignore the backup voltage of search freq #undef DEBUG_ENABLE_I2C_TIMEOUT_PROCESS // if defined, sw will process I2C timeout, but normally FPGA will process timeout, SW do not need this #undef DEBUG_PRINT_T9_PLUS_PIC_HEART_INFO // if defined, used to debug T9+ bug: pic heart cmd failed! #undef DEBUG_PIC_UPGRADE // if defined, we will force to write PIC program data once! #undef DEBUG_KEEP_REBOOT_EVERY_ONE_HOUR // if defined, keep reboot every one hour!!! this is for R4 #undef DEBUG_NOT_CHECK_FAN_NUM // if defined, we will ignore fan number checking, will keep run even without any fan!!! #undef DEBUG_WITHOUT_FREQ_VOLTAGE_LIMIT // if defined, we will not limit freq according to voltage! #undef DEBUG_DOWN_VOLTAGE_TEST #ifdef DEBUG_DOWN_VOLTAGE_TEST #define DEBUG_DOWN_VOLTAGE_VALUE 10 // means down 0.1 V #endif #undef DEBUG_XILINX_NONCE_NOTENOUGH // will disable mutex lock on read temp and send work, but will disable one chain’s read temp #ifdef DEBUG_XILINX_NONCE_NOTENOUGH #define DISABLE_REG_CHAIN_INDEX 5 //disable which chain’s read register #endif #undef DEBUG_OPENCORE_TWICE #undef ENABLE_REINIT_MINING // if defined, will enable hashrate check in mining, and re-init if low hashrate. #undef DEBUG_REINIT // reinit per 2mins and will not do pre heat patten test #undef DEBUG_REBOOT // reboot every 30mins, for test #undef DEBUG_218_FAN_FULLSPEED //for debug on 218, full speed on fan #undef DISABLE_TEMP_PROTECT #undef TWO_CHIP_TEMP_S9 #undef SHOW_BOTTOM_TEMP #undef KEEP_TEMPFAN_LOG // if defined, will not clear old temp fan log info #undef HIGH_TEMP_TEST_S9 //if defined, will use 120 degree as the high temp #undef CAPTURE_PATTEN #define CHECK_RT_IDEAL_RATE_PERCENT 85 // RT rate / ideal rate >= 85% will be OK, or need re init typedef enum { TEMP_POS_LOCAL=0, TEMP_POS_MIDDLE, TEMP_POS_BOTTOM, TEMP_POS_NUM=4, // always the last one, to identify the number of temp , must 4 bytes alignment } TEMP_POSITION; #ifdef R4 #define PWM_T 0 // 0 local temp, 1 middle temp, 2 bottom, as above!!! #define MIN_FAN_NUM 1 #define MAX_FAN_SPEED 3000 #define TEMP_INTERVAL 2 // below are used for R4 on using one app to support C5 and XILINX board extern int MIN_PWM_PERCENT; extern int MID_PWM_PERCENT; extern int MAX_PWM_PERCENT; extern int MAX_TEMP; extern int MAX_FAN_TEMP; extern int MID_FAN_TEMP; extern int MIN_FAN_TEMP; extern int MAX_PCB_TEMP; extern int MAX_FAN_PCB_TEMP; #if PWM_T == 1 #define MIN_PWM_PERCENT_C5 20 #define MID_PWM_PERCENT_C5 60 #define MAX_PWM_PERCENT_C5 100 #define MAX_TEMP_C5 125 #define MAX_FAN_TEMP_C5 110 #define MID_FAN_TEMP_C5 90 #define MIN_FAN_TEMP_C5 60 #define MAX_PCB_TEMP_C5 100 // use middle to control fan, but use pcb temp to check to stop or not! #define MAX_FAN_PCB_TEMP_C5 85 //90 use middle to control fan, but use pcb temp to check to stop or not! #define MIN_PWM_PERCENT_XILINX 20 #define MID_PWM_PERCENT_XILINX 60 #define MAX_PWM_PERCENT_XILINX 100 #define MAX_TEMP_XILINX 125 #define MAX_FAN_TEMP_XILINX 110 #define MID_FAN_TEMP_XILINX 90 #define MIN_FAN_TEMP_XILINX 60 #define MAX_PCB_TEMP_XILINX 100 // use middle to control fan, but use pcb temp to check to stop or not! #define MAX_FAN_PCB_TEMP_XILINX 85 //90 use middle to control fan, but use pcb temp to check to stop or not! #else #define MIN_PWM_PERCENT_C5 50 #define MID_PWM_PERCENT_C5 90 #define MAX_PWM_PERCENT_C5 100 #define MAX_TEMP_C5 90 #define MAX_FAN_TEMP_C5 75 #define MID_FAN_TEMP_C5 65 #define MIN_FAN_TEMP_C5 25 #define MAX_PCB_TEMP_C5 90 // use middle to control fan, but use pcb temp to check to stop or not! #define MAX_FAN_PCB_TEMP_C5 85 //90 use middle to control fan, but use pcb temp to check to stop or not! #define MIN_PWM_PERCENT_XILINX 30 #define MID_PWM_PERCENT_XILINX 70 #define MAX_PWM_PERCENT_XILINX 100 #define MAX_TEMP_XILINX 90 #define MAX_FAN_TEMP_XILINX 75 #define MID_FAN_TEMP_XILINX 65 #define MIN_FAN_TEMP_XILINX 25 #define MAX_PCB_TEMP_XILINX 90 // use middle to control fan, but use pcb temp to check to stop or not! #define MAX_FAN_PCB_TEMP_XILINX 85 //90 use middle to control fan, but use pcb temp to check to stop or not! #endif #define TEMP_INTERVAL 2 #define MID_PWM_ADJUST_FACTOR ((MAX_PWM_PERCENT-MID_PWM_PERCENT)/(MAX_FAN_TEMP-MID_FAN_TEMP)) #define PWM_ADJUST_FACTOR ((MID_PWM_PERCENT-MIN_PWM_PERCENT)/(MID_FAN_TEMP-MIN_FAN_TEMP)) #else // below is for S9 #define PWM_T 1 // 0 local temp, 1 middle temp, 2 bottom, as above!!! #define MIN_FAN_NUM 2 #define MAX_FAN_SPEED 6000 #if PWM_T == 1 #define MIN_PWM_PERCENT 0 #define MAX_PWM_PERCENT 100 #ifdef HIGH_TEMP_TEST_S9 #define MAX_TEMP 135 //125 135 145 release:135 #define MAX_FAN_TEMP 120 // 115 125 135 release:120 #define MIN_FAN_TEMP 70 //65 75 85 release:70 #define MAX_PCB_TEMP 105 //100 105 110 release:105 #define MAX_FAN_PCB_TEMP 95 //95 100 105 release:95 #define MIN_FAN_PCB_TEMP 45 // Attention: MAX_FAN_PCB_TEMP — MIN_FAN_PCB_TEMP = MAX_FAN_TEMP — MIN_FAN_TEMP #else #ifdef TWO_CHIP_TEMP_S9 #define MAX_TEMP 135 //125 135 145 release:135 #define MAX_FAN_TEMP 120 // 115 125 135 release:120 #define MIN_FAN_TEMP 70 //65 75 85 release:70 #define MAX_PCB_TEMP 105 //100 105 110 release:105 #define MAX_FAN_PCB_TEMP 95 //95 100 105 release:95 #define MIN_FAN_PCB_TEMP 45 // Attention: MAX_FAN_PCB_TEMP — MIN_FAN_PCB_TEMP = MAX_FAN_TEMP — MIN_FAN_TEMP #else #define MAX_TEMP 125 //125 135 145 release:125 #define MAX_FAN_TEMP 90 // 115 125 135 release:115 #define MIN_FAN_TEMP 40 //65 75 85 release:65 #define MAX_PCB_TEMP 90 //100 105 110 release:95 #define MAX_FAN_PCB_TEMP 75 //95 100 105 release:85 #define MIN_FAN_PCB_TEMP 25 // Attention: MAX_FAN_PCB_TEMP — MIN_FAN_PCB_TEMP = MAX_FAN_TEMP — MIN_FAN_TEMP #endif #endif #else #define MIN_PWM_PERCENT 20 #define MAX_PWM_PERCENT 100 #define MAX_TEMP 90 #define MAX_FAN_TEMP 75 #define MIN_FAN_TEMP 35 #define MAX_PCB_TEMP 90 // use middle to control fan, but use pcb temp to check to stop or not! #endif #define TEMP_INTERVAL 2 #define PWM_ADJUST_FACTOR ((MAX_PWM_PERCENT-MIN_PWM_PERCENT)/(MAX_FAN_TEMP-MIN_FAN_TEMP)) #endif #ifdef HIGH_TEMP_TEST_S9 #define MIN_TEMP_CONTINUE_DOWN_FAN 110 // release: 90 #define MAX_TEMP_NEED_UP_FANSTEP 120 // release: 100 if temp is higher than 100, then we need make fan much faster #else #define MIN_TEMP_CONTINUE_DOWN_FAN 80 // release: 90 #define MAX_TEMP_NEED_UP_FANSTEP 85 // release: 100 if temp is higher than 100, then we need make fan much faster #endif #define PWM_SCALE 50 //50: 1M=1us, 20KHz?? //25: 40KHz #define PWM_ADJ_SCALE 9/10 //use for hash test #define TEST_DHASH 0 #define DEVICE_DIFF 8 //use for status check #define MAX_TEMPCHIP_NUM 8 // support 8 chip has temp #define MIN_FREQ 4 // 8:300M 6:250M 4:200M #define MAX_FREQ 100 //850M #define MAX_SW_TEMP_OFFSET —15 #define BMMINER_VERSION 3 // 3 for auto freq, 1 or 2 for normal ( the old version is 0) // for c5, bmminer will detect board type and use it. #define RED_LED_DEV_C5 «/sys/class/leds/hps_led2/brightness« #define GREEN_LED_DEV_C5 «/sys/class/leds/hps_led0/brightness« // for xilinx, bmminer will detect board type and use it. #define RED_LED_DEV_XILINX «/sys/class/gpio/gpio37/value« #define GREEN_LED_DEV_XILINX «/sys/class/gpio/gpio38/value« // S9 , T9, R4 PIC PROGRAM #define PIC_PROGRAM «/etc/config/hash_s8_app.txt« // T9+ PIC PROGRAM #define DSPIC33EP16GS202_PIC_PROGRAM «/etc/config/dsPIC33EP16GS202_app.txt« #define TIMESLICE 60 #ifdef T9_18 #define IIC_ADDR_HIGH_4_BIT (0x04 << 20) #define EEPROM_ADDR_HIGH_4_BIT (0x0A << 20) #define IIC_SELECT(x) ((x & 0x03) << 26) unsigned int get_iic(); unsigned char set_iic(unsigned int data); unsigned char T9_plus_write_pic_iic(bool read, bool reg_addr_valid, unsigned char reg_addr, unsigned char which_iic, unsigned char data); int dsPIC33EP16GS202_jump_to_app_from_loader(unsigned char which_iic); #else #define IIC_ADDR_HIGH_4_BIT (0x0A << 20) #endif struct init_config { uint8_t token_type; uint8_t version; uint16_t length; uint8_t reset :1; uint8_t fan_eft :1; uint8_t timeout_eft :1; uint8_t frequency_eft :1; uint8_t voltage_eft :1; uint8_t chain_check_time_eft :1; uint8_t chip_config_eft :1; uint8_t hw_error_eft :1; uint8_t beeper_ctrl :1; uint8_t temp_ctrl :1; uint8_t chain_freq_eft :1; uint8_t reserved1 :5; uint8_t reserved2[2]; uint8_t chain_num; uint8_t asic_num; uint8_t fan_pwm_percent; uint8_t temperature; uint16_t frequency; uint8_t voltage[2]; uint8_t chain_check_time_integer; uint8_t chain_check_time_fractions; uint8_t timeout_data_integer; uint8_t timeout_data_fractions; uint32_t reg_data; uint8_t chip_address; uint8_t reg_address; uint16_t chain_min_freq; uint16_t chain_max_freq; uint16_t crc; } __attribute__((packed, aligned(4))); struct bitmain_c5_info { cglock_t update_lock; uint8_t data_type; uint8_t version; uint16_t length; uint8_t chip_value_eft :1; uint8_t reserved1 :7; uint8_t chain_num; uint16_t reserved2; uint8_t fan_num; uint8_t temp_num; uint8_t reserved3[2]; uint32_t fan_exist; uint32_t temp_exist; uint16_t diff; uint16_t reserved4; uint32_t reg_value; uint32_t chain_asic_exist[BITMAIN_MAX_CHAIN_NUM][BITMAIN_DEFAULT_ASIC_NUM/32]; uint32_t chain_asic_status[BITMAIN_MAX_CHAIN_NUM][BITMAIN_DEFAULT_ASIC_NUM/32]; uint8_t chain_asic_num[BITMAIN_MAX_CHAIN_NUM]; uint8_t temp[BITMAIN_MAX_CHAIN_NUM]; uint8_t fan_speed_value[BITMAIN_MAX_FAN_NUM]; uint16_t freq[BITMAIN_MAX_CHAIN_NUM]; struct thr_info *thr; pthread_t read_nonce_thr; pthread_mutex_t lock; struct init_config c5_config; int pool_no; struct pool pool0; struct pool pool1; struct pool pool2; uint32_t pool0_given_id; uint32_t pool1_given_id; uint32_t pool2_given_id; uint16_t crc; } __attribute__((packed, aligned(4))); struct part_of_job { uint8_t token_type; // buf[0] uint8_t version; uint16_t reserved; uint32_t length; // buf[1] uint8_t pool_nu; // buf[2] uint8_t new_block :1; uint8_t asic_diff_valid :1; uint8_t reserved1 :6; uint8_t asic_diff; uint8_t reserved2[1]; uint32_t job_id; // buf[3] uint32_t bbversion; // buf[4] uint8_t prev_hash[32]; // buf[5] — buf[12] uint32_t ntime; // buf[13] uint32_t nbit; // buf[14] uint16_t coinbase_len; // buf[15] uint16_t nonce2_offset; uint16_t nonce2_bytes_num; // 4 or 8 bytes // buf[16] uint16_t merkles_num; uint64_t nonce2_start_value; //nonce2 start calculate value. // buf[17] — buf[18] }; //uint8_t coinbase //this is variable //uint8_t merkle_bin[32] * merkles_num //uint16_t crc struct nonce_content { uint32_t job_id; uint32_t work_id; uint32_t header_version; uint64_t nonce2; uint32_t nonce3; uint32_t chain_num; uint8_t midstate[MIDSTATE_LEN]; } __attribute__((packed, aligned(4))); struct nonce { uint8_t token_type; uint8_t version; uint16_t length; uint16_t valid_nonce_num; struct nonce_content nonce_cont[MAX_RETURNED_NONCE_NUM]; uint16_t crc; } __attribute__((packed, aligned(4))); struct all_parameters { unsigned int *current_job_start_address; unsigned int pwm_value; unsigned int chain_exist[BITMAIN_MAX_CHAIN_NUM]; unsigned int timeout; unsigned int fan_exist_map; unsigned int temp_sensor_map; unsigned int nonce_error; unsigned int chain_asic_exist[BITMAIN_MAX_CHAIN_NUM][8]; unsigned int chain_asic_status[BITMAIN_MAX_CHAIN_NUM][8]; signed char chain_asic_temp_num[BITMAIN_MAX_CHAIN_NUM]; // the real number of temp chip unsigned char TempChipType[BITMAIN_MAX_CHAIN_NUM][MAX_TEMPCHIP_NUM]; unsigned char TempChipAddr[BITMAIN_MAX_CHAIN_NUM][MAX_TEMPCHIP_NUM]; // each temp chip’s address: chip index*4, index start from 0 int16_t chain_asic_temp[BITMAIN_MAX_CHAIN_NUM][MAX_TEMPCHIP_NUM][TEMP_POS_NUM]; // 4 kinds of temp int16_t chain_asic_maxtemp[BITMAIN_MAX_CHAIN_NUM][TEMP_POS_NUM]; // 4 kinds of temp int16_t chain_asic_mintemp[BITMAIN_MAX_CHAIN_NUM][TEMP_POS_NUM]; // 4 kinds of temp int8_t chain_asic_iic[CHAIN_ASIC_NUM]; uint32_t chain_hw[BITMAIN_MAX_CHAIN_NUM]; uint64_t chain_asic_nonce[BITMAIN_MAX_CHAIN_NUM][BITMAIN_DEFAULT_ASIC_NUM]; char chain_asic_status_string[BITMAIN_MAX_CHAIN_NUM][BITMAIN_DEFAULT_ASIC_NUM+8]; unsigned long long int total_nonce_num; unsigned char fan_exist[BITMAIN_MAX_FAN_NUM]; unsigned int fan_speed_value[BITMAIN_MAX_FAN_NUM]; int temp[BITMAIN_MAX_CHAIN_NUM]; uint8_t chain_asic_num[BITMAIN_MAX_CHAIN_NUM]; unsigned char check_bit; unsigned char pwm_percent; unsigned char chain_num; unsigned char fan_num; unsigned char temp_num; unsigned int fan_speed_top1; int temp_top1[TEMP_POS_NUM]; int temp_low1[TEMP_POS_NUM]; int temp_top1_last; unsigned char corenum; unsigned char addrInterval; unsigned char max_asic_num_in_one_chain; unsigned char baud; unsigned char diff; uint8_t fan_eft; uint8_t fan_pwm; unsigned short int frequency; char frequency_t[10]; unsigned short int freq[BITMAIN_MAX_CHAIN_NUM]; } __attribute__((packed, aligned(4))); struct nonce_buf { unsigned int p_wr; unsigned int p_rd; unsigned int nonce_num; struct nonce_content nonce_buffer[MAX_NONCE_NUMBER_IN_FIFO]; } __attribute__((packed, aligned(4))); struct reg_content { unsigned int reg_value; unsigned char crc; unsigned char chain_number; } __attribute__((packed, aligned(4))); struct reg_buf { unsigned int p_wr; unsigned int p_rd; unsigned int reg_value_num; struct reg_content reg_buffer[MAX_NONCE_NUMBER_IN_FIFO]; } __attribute__((packed, aligned(4))); struct freq_pll { const char *freq; unsigned int fildiv1; unsigned int fildiv2; unsigned int vilpll; }; #define Swap32(l) (((l) >> 24) | (((l) & 0x00ff0000) >> 8) | (((l) & 0x0000ff00) << 8) | ((l) << 24)) struct vil_work { uint8_t type; // Bit[7:5]: Type,fixed 0x01. Bit[4:0]:Reserved uint8_t length; // data length, from Byte0 to the end. uint8_t wc_base; // Bit[7]: Reserved. Bit[6:0]: Work count base, muti-Midstate, each Midstate corresponding work count increase one by one. uint8_t mid_num; // Bit[7:3]: Reserved Bit[2:0]: MSN, midstate num,now support 1,2,4. //uint32_t sno; // SPAT mode??Start Nonce Number Normal mode??Reserved. uint8_t midstate[32]; uint8_t data2[12]; }; struct vil_work_1387 { uint8_t work_type; uint8_t chain_id; uint8_t reserved1[2]; uint32_t work_count; uint8_t data[12]; uint8_t midstate[32]; }; static struct freq_pll freq_pll_1385[] = { {«100«,0x020040, 0x0420, 0x200241}, {«125«,0x028040, 0x0420, 0x280241}, {«150«,0x030040, 0x0420, 0x300241}, {«175«,0x038040, 0x0420, 0x380241}, {«200«,0x040040, 0x0420, 0x400241}, {«225«,0x048040, 0x0420, 0x480241}, {«250«,0x050040, 0x0420, 0x500241}, {«275«,0x058040, 0x0420, 0x580241}, {«300«,0x060040, 0x0420, 0x600241}, {«325«,0x068040, 0x0420, 0x680241}, {«350«,0x070040, 0x0420, 0x700241}, {«375«,0x078040, 0x0420, 0x780241}, {«400«,0x080040, 0x0420, 0x800241}, {«404«,0x061040, 0x0320, 0x610231}, {«406«,0x041040, 0x0220, 0x410221}, {«408«,0x062040, 0x0320, 0x620231}, {«412«,0x042040, 0x0220, 0x420221}, {«416«,0x064040, 0x0320, 0x640231}, {«418«,0x043040, 0x0220, 0x430221}, {«420«,0x065040, 0x0320, 0x650231}, {«425«,0x044040, 0x0220, 0x440221}, {«429«,0x067040, 0x0320, 0x670231}, {«431«,0x045040, 0x0220, 0x450221}, {«433«,0x068040, 0x0320, 0x680231}, {«437«,0x046040, 0x0220, 0x460221}, {«441«,0x06a040, 0x0320, 0x6a0231}, {«443«,0x047040, 0x0220, 0x470221}, {«445«,0x06b040, 0x0320, 0x6b0231}, {«450«,0x048040, 0x0220, 0x480221}, {«454«,0x06d040, 0x0320, 0x6d0231}, {«456«,0x049040, 0x0220, 0x490221}, {«458«,0x06e040, 0x0320, 0x6e0231}, {«462«,0x04a040, 0x0220, 0x4a0221}, {«466«,0x070040, 0x0320, 0x700231}, {«468«,0x04b040, 0x0220, 0x4b0221}, {«470«,0x071040, 0x0320, 0x710231}, {«475«,0x04c040, 0x0220, 0x4c0221}, {«479«,0x073040, 0x0320, 0x730231}, {«481«,0x04d040, 0x0220, 0x4d0221}, {«483«,0x074040, 0x0320, 0x740231}, {«487«,0x04e040, 0x0220, 0x4e0221}, {«491«,0x076040, 0x0320, 0x760231}, {«493«,0x04f040, 0x0220, 0x4f0221}, {«495«,0x077040, 0x0320, 0x770231}, {«500«,0x050040, 0x0220, 0x500221}, {«504«,0x079040, 0x0320, 0x790231}, {«506«,0x051040, 0x0220, 0x510221}, {«508«,0x07a040, 0x0320, 0x7a0231}, {«512«,0x052040, 0x0220, 0x520221}, {«516«,0x07c040, 0x0320, 0x7c0231}, {«518«,0x053040, 0x0220, 0x530221}, {«520«,0x07d040, 0x0320, 0x7d0231}, {«525«,0x054040, 0x0220, 0x540221}, {«529«,0x07f040, 0x0320, 0x7f0231}, {«531«,0x055040, 0x0220, 0x550221}, {«533«,0x080040, 0x0320, 0x800231}, {«537«,0x056040, 0x0220, 0x560221}, {«543«,0x057040, 0x0220, 0x570221}, {«550«,0x058040, 0x0220, 0x580221}, {«556«,0x059040, 0x0220, 0x590221}, {«562«,0x05a040, 0x0220, 0x5a0221}, {«568«,0x05b040, 0x0220, 0x5b0221}, {«575«,0x05c040, 0x0220, 0x5c0221}, {«581«,0x05d040, 0x0220, 0x5d0221}, {«587«,0x05e040, 0x0220, 0x5e0221}, {«593«,0x05f040, 0x0220, 0x5f0221}, {«600«,0x060040, 0x0220, 0x600221}, {«606«,0x061040, 0x0220, 0x610221}, {«612«,0x062040, 0x0220, 0x620221}, {«618«,0x063040, 0x0220, 0x630221}, {«625«,0x064040, 0x0220, 0x640221}, {«631«,0x065040, 0x0220, 0x650221}, {«637«,0x066040, 0x0220, 0x660221}, {«643«,0x067040, 0x0220, 0x670221}, {«650«,0x068040, 0x0220, 0x680221}, {«656«,0x069040, 0x0220, 0x690221}, {«662«,0x06a040, 0x0220, 0x6a0221}, {«668«,0x06b040, 0x0220, 0x6b0221}, {«675«,0x06c040, 0x0220, 0x6c0221}, {«681«,0x06d040, 0x0220, 0x6d0221}, {«687«,0x06e040, 0x0220, 0x6e0221}, {«693«,0x06f040, 0x0220, 0x6f0221}, {«700«,0x070040, 0x0220, 0x700221}, {«706«,0x071040, 0x0220, 0x710221}, {«712«,0x072040, 0x0220, 0x720221}, {«718«,0x073040, 0x0220, 0x730221}, {«725«,0x074040, 0x0220, 0x740221}, {«731«,0x075040, 0x0220, 0x750221}, {«737«,0x076040, 0x0220, 0x760221}, {«743«,0x077040, 0x0220, 0x770221}, {«750«,0x078040, 0x0220, 0x780221}, {«756«,0x079040, 0x0220, 0x790221}, {«762«,0x07a040, 0x0220, 0x7a0221}, {«768«,0x07b040, 0x0220, 0x7b0221}, {«775«,0x07c040, 0x0220, 0x7c0221}, {«781«,0x07d040, 0x0220, 0x7d0221}, {«787«,0x07e040, 0x0220, 0x7e0221}, {«793«,0x07f040, 0x0220, 0x7f0221}, {«800«,0x080040, 0x0220, 0x800221}, {«825«,0x042040, 0x0120, 0x420211}, {«850«,0x044040, 0x0120, 0x440211}, {«875«,0x046040, 0x0120, 0x460211}, {«900«,0x048040, 0x0120, 0x480211}, {«925«,0x04a040, 0x0120, 0x4a0211}, {«950«,0x04c040, 0x0120, 0x4c0211}, {«975«,0x04e040, 0x0120, 0x4e0211}, {«1000«,0x050040, 0x0120, 0x500211}, {«1025«,0x052040, 0x0120, 0x520211}, {«1050«,0x054040, 0x0120, 0x540211}, {«1075«,0x056040, 0x0120, 0x560211}, {«1100«,0x058040, 0x0120, 0x580211}, {«1125«,0x05a040, 0x0120, 0x5a0211}, {«1150«,0x05c040, 0x0120, 0x5c0211}, {«1175«,0x05e040, 0x0120, 0x5e0211}, }; extern bool opt_bitmain_fan_ctrl; extern bool opt_bitmain_new_cmd_type_vil; extern bool opt_fixed_freq; extern bool opt_pre_heat; extern int opt_bitmain_fan_pwm; extern int opt_bitmain_c5_freq; extern int opt_bitmain_c5_voltage; extern int ADD_FREQ; extern int ADD_FREQ1; extern int fpga_version; #endif