Ошибка 10500 vhdl

The reserved word signal is required signal declarations in these block declarative items:

end component;

    signal x: std_logic;
    signal i: std_logic_vector(4 downto 0);  -- added reserved word signal
    signal ta , tb , tc: std_logic;          -- added reserved word signal
    signal tap , tbp , tcp: std_logic;       -- added reserved word signal

begin

Those get rid of your 10500 syntax errors, (there are more):

ghdl -a tl2.vhdl
tl2.vhdl:31:36: no declaration for «clock»
tl2.vhdl:31:51: no declaration for «clear»
tl2.vhdl:31:66: no declaration for «count»
tl2.vhdl:31:79: no declaration for «q»
tl2.vhdl:32:24: no declaration for «clock»
tl2.vhdl:32:38: no declaration for «t»
tl2.vhdl:32:49: no declaration for «output»
tl2.vhdl:33:24: no declaration for «clock»
tl2.vhdl:33:38: no declaration for «t»
tl2.vhdl:33:49: no declaration for «output»
tl2.vhdl:34:24: no declaration for «clock»
tl2.vhdl:34:38: no declaration for «t»
tl2.vhdl:34:49: no declaration for «output»
tl2.vhdl:36:12: signal «i» does not designate a record
tl2.vhdl:42:13: no declaration for «clear»

Your formals and actuals were reversed in your component instantiations:

counter4: 
counter port map ( 
            clock => clk,
            clear => '0',
            count => '1',
            Q =>i
        );
            --- clk => clock , '0' => clear , '1' => count , i => Q);
A: 
    tff 
        port map (
            clock => clk,
            t => ta,
            output => tap
        );
            -- clk => clock , ta => t , tap => output);
B: 
    tff 
        port map (
            clock => clk,
            t => tb,
            output => tbp
        );
            -- clk => clock , tb => t , tbp => output);
C: 
    tff 
        port map (
            clock => clk,
            t => tc,
            output => tcp
            );
            --  clk => clock , tc => t , tcp => output);

Notice that with named association the order doesn’t have to match component declarations.

tl2.vhdl:64:12: signal «i» does not designate a record:

    process( i,tap,tbp, tcp, x )          -- process( i.ta,tb,tc )
    begin
        if i = "00011" or i = "00110" or i = "10101"  then
            x <= '1';
        end if;
        if  i = "10101" then
            clear <= '0';
        end if;
        ta <= ((tbp and tcp and x)or(tap and tcp and x));
        tb <= (not tap and tcp and x);
        tc <= x;

    end process;

Note that every signal from the right hand side of a signal assignment or evaluated in an if statement condition expression has been added to the sensitivity list. (And about now someone is bound to pipe in that in VHDL 2008 you could use the keyword all in place of individual elements in the sensitivity list).

ghdl -a tl2.vhdl
tl2.vhdl:70:13: no declaration for «clear»

Notice clear is defined as an input to tl2. Did you mean an assignment to x here:

    if( i="10101" ) then
        x <= '0';          -- clear <= '0';
    end if;

You could also note that no where do you have an assignment to i. The default value for i would be «UUUUU» which would guarantee none of the condition evaluations in the if statements would result in an assignment. You need to play ‘Where’s Waldo’ with i yet.

It isn’t clear how sharth mutilated the code example, it appears he accepted a just-checking-you-were-paying-attention test case blindly. (I restored it, before someone down voted your question, before I save this answer).

Error 10500 is a catch all syntax error, where one could imagine the preposition is that someone would resort to authoritative VHDL texts (e.g. the LRM) to resolve issues with syntax. In general error messages don’t teach languages and it’s an extra effort to analyze syntax errors for an actual cause, not required by the VHDL standard where a VHDL design specification can be analyzed with a look ahead of one lexical token.

You can see from the text of the first error message it interpreted i: as a label which can precede any statement — other than a declarative item. The error message leaves something to be desired. The second error text is no more enlightening than the first.

The fault lies in the quality of error messages and likely reinforces the idea that the user will at least resort to a syntax summary to resolve syntax errors. See Hyperlinked VHDL-93 BNF Syntax or EBNF Syntax: VHDL’93 (I don’t currently know of a useful syntax summary for VHDL-2008).

Using the EBNF as a reference has the interesting side effect of giving us common language to discuss VHDL syntax, useful for describing errors and fixes.

I am working on a code for a basic vending machine that will give out a product at 75cents 

BUt for some reason I dont know how to fix this syntax error 


Library ieee;
Use ieee.numeric_std.all;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity Lab06 is
Port (
Clock :IN std_logic;
Reset_n :IN std_logic;
Quarter_in :IN std_logic;
Dime_in :IN std_logic;
Nickel_in :IN std_logic;
Pennny_in :IN std_logic;
Coin_Return :IN std_logic);
End Lab06;
Architecture Behavior Of Lab06 is
Signal int_counter: std_logic_vector(25 downto 0);
Constant MAXVALUE: std_logic_vector(25 downto 0):= "10111110101111000010000000"; --One Second Count
-------------------------------------------------------------------------------------------------
Type State_type is (wait1, penny, dime, nickel, quarter, enough, excess, vend, change);
Signal current_state,next_state: state_type;
Signal Money: std_logic_vector(6 downto 0);
Signal Red_Bull: std_logic;
Signal Change_Back: std_logic;
Begin
Counter_Clock:Process (clock, reset_n)
Begin
If reset_n = '0' Then
Int_counter <= (Others => '0');
Elsif (rising_edge(clock)) Then
If int_counter = MAXVALUE Then
int_counter <= (Others => '0');
Else
int_counter <= int_counter + '1';
End If;
End If;
End Process;
Sync:Process (clock, reset_n)
Begin
If (reset_n = '0')then
Current_state <= Wait1;--Wait1 is the default state_type
Elsif(rising_edge(clock))Then
If (int_counter = MAXVALUE)Then
Current_state <=next_state;-- Advance the state(Red Bull)machine
End If;
End If;
End Process;
Comb:Process(int_counter,current_state, Quarter_in, Dime_in, Nickel_in, Pennny_in, money, Coin_Return)
Begin
If (int_counter = MAXVALUE) Then
Case(current_state)is
When wait1=>
If (money = "0000000")Then -- No money in vending machine
next_state <= Wait1;
If (Quarter_in = '1')Then -- Money is inserted
next_state <= Quarter;
If (Dime_in = '1')Then
next_state <= Dime;
If (Nickel_in = '1')Then
next_state <= Nickel;
If (Pennny_in = '1')Then
next_state <= Penny;
If (money >= "1001011")Then
next_state <= Enough;
If(Coin_Return = '1')Then
next_state <= Change;
Else
next_state <=Wait1;
End If;
----------------------------------------------------------------- After Quarter Inserted, next step
When Quarter =>
Next_state <= Wait1;
----------------------------------------------------------------- After Dime Inserted, next step
When Dime =>
Next_state <= Wait1;
----------------------------------------------------------------- After Nickel Inserted, next step
When Nickel =>
Next_state <= Wait1;
----------------------------------------------------------------- After Penny Inserted, next step
When Penny =>
Next_state <= Wait1;

When Enough =>
If (money >= "1001011")Then
Next_state <= Excess;
Else
Next_state <= vend;
End If;
When Excess =>
Next_state <= vend;
When vend =>
Next_state <= Wait1;
When Change =>
Next_state <= Wait1;
When OTHERS =>
next_state <= Wait1;
End Case;
End If;
End Process;
----------------------------------------------------------------- Money calculation
Money_Calc:Process(Current_state, money)
Begin
Case (current_state) is
When wait1 =>
Money <= Money;
When Quarter =>
Money <= Money + "0011001";
When Dime =>
Money <= Money + "0001010";
When Nickel =>
Money <= Money + "0000101";
When Penny =>
Money <= Money + "0000001";
When Enough =>
Money <= money;
When Excess =>
Money <= Money;
When vend =>
Money <= Money - "1001011";
When change =>
Money <= "0000000";
When OTHERS =>
Money <= Money;
End Case;
End Process;
End Behavior;


The errors I am getting are 

Info: ******************************************************************* 

Info: Running Quartus II 32-bit Analysis & Synthesis 

Info: Version 12.0 Build 178 05/31/2012 SJ Full Version 

Info: Processing started: Wed Oct 31 15:32:29 2012 

Info: Command: quartus_map —read_settings_files=on —write_settings_files=off Lab06 -c Lab06 

Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected 

Info (12021): Found 2 design units, including 1 entities, in source file hex_display.vhd 

Info (12022): Found design unit 1: Hex_Display-Structure 

Info (12023): Found entity 1: Hex_Display 

Error (10500): VHDL syntax error at Lab06.vhd(108) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement 

Error (10500): VHDL syntax error at Lab06.vhd(111) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement 

Error (10500): VHDL syntax error at Lab06.vhd(114) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement 

Error (10500): VHDL syntax error at Lab06.vhd(117) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement 

Error (10500): VHDL syntax error at Lab06.vhd(120) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement 

Error (10500): VHDL syntax error at Lab06.vhd(126) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement 

Error (10500): VHDL syntax error at Lab06.vhd(128) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement 

Error (10500): VHDL syntax error at Lab06.vhd(130) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement 

Error (10500): VHDL syntax error at Lab06.vhd(132) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement 

Error (10500): VHDL syntax error at Lab06.vhd(134) near text «Case»; expecting «if» 

Error (10500): VHDL syntax error at Lab06.vhd(136) near text «Process»; expecting «if» 

Error (10500): VHDL syntax error at Lab06.vhd(139) near text «Begin»; expecting «:=», or «<=» 

Error (10500): VHDL syntax error at Lab06.vhd(162) near text «Process»; expecting «if» 

Info (12021): Found 0 design units, including 0 entities, in source file lab06.vhd 

Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 13 errors, 0 warnings 

Any assistance would be very helpful.

У меня проблема с этим кодом !!!

library ieee ;
use ieee.std_logic_1164.all;

entity tl2 is
port( clk: in std_logic );
end tl2;

architecture ways2 of tl2 is
component counter is
generic(
n: natural :=5
); port(
clock:  in std_logic;
clear:  in std_logic;
count:  in std_logic;
Q:  out std_logic_vector(n-1 downto 0)
);
end component;

component tff is
port(
t: in  std_logic;
clock: in std_logic;
output: out std_logic
);
end component;

signal x: std_logic;
i: std_logic_vector(4 downto 0);
ta , tb , tc: std_logic;
tap , tbp , tcp: std_logic;

begin

counter4: counter port map( clk => clock , '0' => clear , '1' => count , i => Q);
A: tff port map(clk => clock , ta => t , tap => output);
B: tff port map(clk => clock , tb => t , tbp => output);
C: tff port map(clk => clock , tc => t , tcp => output);

process( i.ta,tb,tc )
begin
if( i="00011" or i="00110" or i="10101" ) then
x <= '1';
end if;
if( i="10101" ) then
clear <= '0';
end if;
ta <= ((tbp and tcp and x)or(tap and tcp and x));
tb <= (not tap and tcp and x);
tc <= x;

end process;

end ways2;

user3139746 подробно объяснил ошибки, о которых он просил в комментарии в ответ на комментарий к sharth:

thats error: Error (10500): Синтаксическая ошибка VHDL при tl2.vhd(27) возле текста “i”; ожидая “начало” или выражение объявления Ошибка (10500): синтаксическая ошибка VHDL в tl2.vhd(33) возле текста “=>”; Ожидание “)”, или “,” – user3139746 4 часа назад

(Это сообщение об ошибке Altera)

Зарезервированный словарный сигнал – это обязательные декларации сигналов в этих декларативных элементах блока:

end component;

signal x: std_logic;
signal i: std_logic_vector(4 downto 0);  -- added reserved word signal
signal ta , tb , tc: std_logic;          -- added reserved word signal
signal tap , tbp , tcp: std_logic;       -- added reserved word signal

begin

Они избавляются от ваших синтаксических ошибок 10500 (их больше):

ghdl -a tl2.vhdl
tl2.vhdl: 31: 36: нет объявления для “часов”
tl2.vhdl: 31: 51: нет декларации для “четких”
tl2.vhdl: 31: 66: нет декларации для “count”
tl2.vhdl: 31: 79: нет объявления для “q”
tl2.vhdl: 32: 24: нет объявления для “часов”
tl2.vhdl: 32: 38: нет объявления для “t”
tl2.vhdl: 32: 49: нет декларации для “output”
tl2.vhdl: 33: 24: нет объявления для “часов”
tl2.vhdl: 33: 38: нет декларации для “t”
tl2.vhdl: 33: 49: нет декларации для “output”
tl2.vhdl: 34: 24: нет декларации для “часов”
tl2.vhdl: 34: 38: нет объявления для “t”
tl2.vhdl: 34: 49: нет декларации для “вывода”
tl2.vhdl: 36: 12: сигнал “i” не обозначает запись
tl2.vhdl: 42: 13: нет декларации для “четких”

Ваши форматы и фактические данные были отменены в ваших экземплярах компонентов:

counter4:
counter port map (
clock => clk,
clear => '0',
count => '1',
Q =>i
);
--- clk => clock , '0' => clear , '1' => count , i => Q);
A:
tff
port map (
clock => clk,
t => ta,
output => tap
);
-- clk => clock , ta => t , tap => output);
B:
tff
port map (
clock => clk,
t => tb,
output => tbp
);
-- clk => clock , tb => t , tbp => output);
C:
tff
port map (
clock => clk,
t => tc,
output => tcp
);
--  clk => clock , tc => t , tcp => output);

Обратите внимание, что при именованной ассоциации заказ не должен соответствовать объявлениям компонентов.

tl2.vhdl: 64: 12: сигнал “i” не обозначает запись:

    process( i,tap,tbp, tcp, x )          -- process( i.ta,tb,tc )
begin
if i = "00011" or i = "00110" or i = "10101"  then
x <= '1';
end if;
if  i = "10101" then
clear <= '0';
end if;
ta <= ((tbp and tcp and x)or(tap and tcp and x));
tb <= (not tap and tcp and x);
tc <= x;

end process;

Обратите внимание, что каждый сигнал с правой стороны назначения сигнала или оценивается в выражении условия оператора if, добавлен в список чувствительности. (И вот теперь кто-то связан с трубой, поскольку в VHDL 2008 вы можете использовать ключевое слово all вместо отдельных элементов в списке чувствительности).

ghdl -a tl2.vhdl
tl2.vhdl: 70: 13: нет декларации для “четких”

Уведомление clear определено как вход для tl2. Вы имели в виду назначение x здесь:

    if( i="10101" ) then
x <= '0';          -- clear <= '0';
end if;

Вы также можете отметить, что нет, где у вас есть задание на i. Значение по умолчанию для я будет “UUUUU”, которое гарантировало бы, что ни одна из оценок условий в операторах if не приведет к присвоению. Вы должны играть “Где Уолдо” с i еще.

Непонятно, как искалечил рисунок пример кода, похоже, он слепо посмотрел на проверочный тестовый тест -a. (Я восстановил его, прежде чем кто-то проголосовал за ваш вопрос, прежде чем я сохраню этот ответ).

Ошибка 10500 – это ошибка синтаксиса catch, где можно предположить, что предлог заключается в том, что кто-то прибегает к авторитетным текстам VHDL (например, LRM) для решения проблем с синтаксисом. В общих сообщениях об ошибках не преподаются языки, и это требует дополнительных усилий для анализа синтаксических ошибок по фактической причине, не требуемых стандартом VHDL, где спецификация дизайна VHDL может быть проанализирована, если смотреть на один лексический токен.

Вы можете видеть из текста первого сообщения об ошибке, которое оно интерпретировало i: как ярлык, который может предшествовать любому утверждению – кроме декларативного элемента. Сообщение об ошибке оставляет желать лучшего. Второй текст ошибки не более просветляющий, чем первый.

Ошибка связана с качеством сообщений об ошибках и, вероятно, усиливает мысль о том, что пользователь, по крайней мере, прибегнет к резюме синтаксиса для устранения синтаксических ошибок. См. Синтаксис BNF с гиперссылками VHDL-93 или синтаксис EBNF: VHDL’93 (в настоящее время я не знаю полезного резюме синтаксиса для VHDL-2008).

Использование EBNF в качестве ссылки имеет интересный побочный эффект, давая нам общий язык для обсуждения синтаксиса VHDL, полезный для описания ошибок и исправлений.

Vhdl syntax error near begin

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Error 10500: VHDL Syntax

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I am working on a code for a basic vending machine that will give out a product at 75cents

BUt for some reason I dont know how to fix this syntax error

Library ieee; Use ieee.numeric_std.all; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity Lab06 is Port ( Clock :IN std_logic; Reset_n :IN std_logic; Quarter_in :IN std_logic; Dime_in :IN std_logic; Nickel_in :IN std_logic; Pennny_in :IN std_logic; Coin_Return :IN std_logic); End Lab06; Architecture Behavior Of Lab06 is Signal int_counter: std_logic_vector(25 downto 0); Constant MAXVALUE: std_logic_vector(25 downto 0):= «10111110101111000010000000»; —One Second Count ————————————————————————————————- Type State_type is (wait1, penny, dime, nickel, quarter, enough, excess, vend, change); Signal current_state,next_state: state_type; Signal Money: std_logic_vector(6 downto 0); Signal Red_Bull: std_logic; Signal Change_Back: std_logic; Begin Counter_Clock:Process (clock, reset_n) Begin If reset_n = ‘0’ Then Int_counter ‘0’); Elsif (rising_edge(clock)) Then If int_counter = MAXVALUE Then int_counter ‘0’); Else int_counter If (money = «0000000»)Then — No money in vending machine next_state = «1001011»)Then next_state Next_state Next_state Next_state Next_state If (money >= «1001011»)Then Next_state Next_state Next_state Next_state next_state Money Money Money Money Money Money Money Money Money Money

The errors I am getting are

Info: Running Quartus II 32-bit Analysis & Synthesis

Info: Version 12.0 Build 178 05/31/2012 SJ Full Version

Info: Processing started: Wed Oct 31 15:32:29 2012

Info: Command: quartus_map —read_settings_files=on —write_settings_files=off Lab06 -c Lab06

Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected

Info (12021): Found 2 design units, including 1 entities, in source file hex_display.vhd

Info (12022): Found design unit 1: Hex_Display-Structure

Info (12023): Found entity 1: Hex_Display

Error (10500): VHDL syntax error at Lab06.vhd(108) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(111) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(114) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(117) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(120) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(126) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(128) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(130) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(132) near text «When»; expecting «end», or «(«, or an identifier («when» is a reserved keyword), or a sequential statement

Error (10500): VHDL syntax error at Lab06.vhd(134) near text «Case»; expecting «if»

Error (10500): VHDL syntax error at Lab06.vhd(136) near text «Process»; expecting «if»

Error (10500): VHDL syntax error at Lab06.vhd(139) near text «Begin»; expecting «:=», or » 0 баллов

Источник

Why I have If-then VHDL errors in my code?

Opel_Corsa

Member level 1

epoxi

Newbie level 2

mmh, strange, I’ll check that

bakkali

Junior Member level 1

if else in vhdl

first i think that you miss a «end if» in your code
you have two if so you mast write two end if
i wish to view all the code if you can

Girisha

Newbie level 2

vhdl if statement outside process

U have write sequential statements inside the process.
The if else statements are sequential statements. so u need to write these statements inside the process.
I think u r trying to write state mechine it should be change the state with respect to clock,
include clock event statements in process sensitivity list, u can refer any VHDL state mechine examples.

rsrinivas

Advanced Member level 1

vhdl if then else

if(m==load) is the correct syntax
if(condition)
u r using
if(assignment)
as girisha told make sure ur if part is in a process

lucbra

Advanced Member level 2

vhdl illegal sequential statement

There is missing a begin statement after the type and signal declarations.

Opel_Corsa

Member level 1

error (10500) vhdl

Thanks very much for all the responses. First, the code that I posted was not a state machine. My code does deal with a state machine, but the one posted wasn’t one. Also there are correct number of «end if» statements in my code. In any case, here’s the full part of the architecture (the code is still incomplete, but I think it should compile nevertheless):

Elephantus

Junior Member level 3

Is a sequential statement, not a concurrent one, and cannot be written outside a process begin/end block. Therefore, you can write it as:

Or, you might use the concurrent assignment form:

which can be safely written in an architecture body.

Hope this helps.

Opel_Corsa

Member level 1

vhdl if condition

Thanks. Can you explain why you are considering m to be a clock? (since the if-then clause is sequential). I thought it was purely combinational.

rsrinivas

Advanced Member level 1

syntax of if statement in vhdl

if is a sequential statement and it should be present in a process.
But when u synthesise if statements it becomes MUX which is combinational.

Elephantus

Junior Member level 3

error (10500): vhdl

In this process, m is not a clock. Synchronous (clocked) logic is described in a different manner in VHDL.

When you define a process:

The signals in the parentheses are the members of the process’ sensitivity list. This means that the sequential statements in the process will re-execute and re-evaluate on any change of any signal in the list. The code described above is a purely combinatorial process:
The general rule is: when you describe complex combinatorial functions in VHDL, use processes and assign ALL inputs of the combinatorial process to the sensitivity list.

Synchronous processes (registers) need to trigger only on a rising or falling edge of a clock signal.

The process above describes a d type flip flop which samples the input d on the rising edge of clk. Note that only the global set-reset (gsr) and the clock signal are in the process sensitivity list. That’s because these are the only signals the process must react to. As you can see, the presence of the clk signal in the sensitivity list is not sufficient to make it a clock signal. The condition that the change happens at rising_edge(clk) makes clk a clock signal, and the synthesis tools recognize clk as a clock signal through the rising edge condition.

The general rule would be: When describing synchronous logic, use processes triggered by a clk and an async reset signal (if needed), and make the assignment conditional by the rising_edge(clk) or falling_edge(clk). (see code above)

Also, don’t mix sequential statements with sequential logic. VHDL as a language consists of sequential statements (which are executed in order) and concurrent statements (which are executed in parallel). Sequential statements do not directly correspond with sequential(synchronous) logic.

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