Syntax error unexpected integer number

You mean error file? I suppose modelsim creates this. 

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors
// are exported from a vector file in the Quartus Waveform Editor and apply to
// the top level entity of the current Quartus project .The user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// Generated on "12/17/2013 11:18:31"

begin
if ($realtime > 0)
begin
if ($realtime == 0 || $realtime != current_time)
begin
if (sample === 1'bx)
sample = 0;
else
sample = ~sample;
end
current_time = $realtime;
end
end
assign sampler_tx = sample;
endmodule
module freq_dev_vlg_check_tst (
output,
sampler_rx
);
input output;
input sampler_rx;
reg output_expected;
reg output_prev;
reg output_expected_prev;
reg last_output_exp;
reg trigger;
integer i;
integer nummismatches;
reg on_first_change ;
initial
begin
trigger = 0;
i = 0;
nummismatches = 0;
on_first_change = 1'b1;
end
// update real /o prevs
always @(trigger)
begin
output_prev = output;
end
// update expected /o prevs
always @(trigger)
begin
output_expected_prev = output_expected;
end
// expected output
initial
begin
output_expected = 1'bX;
end
// generate trigger
always @(output_expected or output)
begin
trigger <= ~trigger;
end
always @(posedge sampler_rx or negedge sampler_rx)
begin
`ifdef debug_tbench
$display("Scanning pattern %d @time = %t",i,$realtime );
i = i + 1;
$display("| expected output = %b | ",output_expected_prev);
$display("| real output = %b | ",output_prev);
`endif
if (
( output_expected_prev !== 1'bx ) && ( output_prev !== output_expected_prev )
&& ((output_expected_prev !== last_output_exp) ||
on_first_change)
)
begin
$display ("ERROR! Vector Mismatch for output port output :: @time = %t", $realtime);
$display (" Expected value = %b", output_expected_prev);
$display (" Real value = %b", output_prev);
nummismatches = nummismatches + 1;
on_first_change = 1'b0;
last_output_exp = output_expected_prev;
end
trigger <= ~trigger;
end
initial
begin
$timeformat(-12,3," ps",6);
# 1000000;
if (nummismatches > 0)
$display ("%d mismatched vectors : Simulation failed !",nummismatches);
else
$display ("Simulation passed !");
$finish;
end
endmodule
module freq_dev_vlg_vec_tst();
// constants
// general purpose registers
reg input;
// wires
wire output;
wire sampler;
// assign statements (if any)
freq_dev i1 (
// port map - connection between master ports and signals/registers
.input (input),
.output (output)
);
// input
always
begin
input = 1'b0;
input =# 25000 1'b1;
# 25000;
end
freq_dev_vlg_sample_tst tb_sample (
.input(input),
.sampler_tx(sampler)
);
freq_dev_vlg_check_tst tb_out(
.output(output),
.sampler_rx(sampler)
);
endmodule


Как исправить «Uncaught SyntaxError: Unexpected number», появляющийся только в Chrome?

Я пытаюсь запустить сайт Django, используя Gunicorn (с компоновкой докеров). В Firefox все работает, как и ожидалось, но Chrome сообщает об ошибке «Uncaught SyntaxError: Unexpected number» для случайных скриптов .js. Если я перезагружаю страницу, скрипты загружаются без ошибок.

Итак, сначала у меня была аналогичная проблема, так как Chrome случайным образом не загружал скрипты. Я решил это, изменив порт в Gunicorn с 8080 на 80. Однако, как только я это сделал, скрипты начали загружаться, но также начали выдавать ошибку «Неожиданный номер».

Я протестировал его как на Chromium (Ubuntu 18), так и на Google Chrome (Windows), запустив веб-сайт локально и с сервера.

Кроме того, я заметил следующее:

1) файлы, которые выдают ошибки, редко бывают одинаковыми, поэтому в одном окне скрипт example1.js может работать, а example2.js выдает ошибку, а в другом окне example3.js выдает ошибку, а остальные работают.

2) если я перезагружу страницу, ни один файл .js не выдаст ошибку.

3) каждая ошибка указывает на то, что проблема в строке 5, например: «Uncaught SyntaxError: Unexpected number jquery-3.2.1.min.js:5».

Буду очень признателен за совет, как с этим бороться.

Откройте инструменты разработчика Chrome и нажмите на информацию об ошибке в консоли, чтобы увидеть, какой код на самом деле получил Chrome.

, что возникла проблема с сетью, из-за которой Chrome на самом деле не получает ожидаемые данные.

Спасибо за предложение Эрик. Мне удалось решить проблему, и вы были правы. Как только я добавил nginx в конфигурацию, у меня не было проблем с загрузкой статических файлов. Я не совсем уверен, где именно была проблема, но это решило ее.

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• Re: Syntax error, unexpected integer number, expecting identifier

Syntax error, unexpected integer number, expecting identifier

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Hello there. I am starter at FPGA. I’ve advanced digital design course at my M.Sc class. Lecturer give us a homework about on Quartus 2,creating schematic designs, graphical test vector and simulate it, simulating it via Modelsim at impelement designs to DE2 board and obversing the results. There are my schematic design, pin assigments and when I tried to make a functional simulating at waveform graph I got an error. Don’t get confuse with the name of project. At firs I intended to design a 2×1 Mux with logic gates but then I just designed a simple circuit like that. What is my problem?

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the problem is that you named the project 21mux. To work in modelsim it has to convert the schematic to an HDL (VHDL or verilog), which appears to be verilog in your case. Neither HDL allow names to start with numbers.

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I am very grateful to you Sir. Thanks for help. I was near to destroy my laptop because of this error. I open new project and named it as » multip » and it worked.

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I’m having relative problem, the error text is:

# ** Error: Waveform.vwf.vt(30): near «,»: syntax error, unexpected ‘,’# ** Error: C:/modeltech64_10.1c/win64/vlog failed.# Executing ONERROR command at macro ./freq.do line 4

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You didnt show the code with the error.

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You mean error file? I suppose modelsim creates this.

// Copyright (C) 1991-2013 Altera Corporation // Your use of Altera Corporation’s design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // ***************************************************************************** // This file contains a Verilog test bench with test vectors .The test vectors // are exported from a vector file in the Quartus Waveform Editor and apply to // the top level entity of the current Quartus project .The user can use this // testbench to simulate his design using a third-party simulation tool . // ***************************************************************************** // Generated on «12/17/2013 11:18:31» // Verilog Self-Checking Test Bench (with test vectors) for design : freq_dev // // Simulation tool : 3rd Party // `timescale 1 ps/ 1 ps module freq_dev_vlg_sample_tst( input, sampler_tx ); input input; output sampler_tx; reg sample; time current_time; always @(input) begin if ($realtime > 0) begin if ($realtime == 0 || $realtime != current_time) begin if (sample === 1’bx) sample = 0; else sample =

sample; end current_time = $realtime; end end assign sampler_tx = sample; endmodule module freq_dev_vlg_check_tst ( output, sampler_rx ); input output; input sampler_rx; reg output_expected; reg output_prev; reg output_expected_prev; reg last_output_exp; reg trigger; integer i; integer nummismatches; reg on_first_change ; initial begin trigger = 0; i = 0; nummismatches = 0; on_first_change = 1’b1; end // update real /o prevs always @(trigger) begin output_prev = output; end // update expected /o prevs always @(trigger) begin output_expected_prev = output_expected; end // expected output initial begin output_expected = 1’bX; end // generate trigger always @(output_expected or output) begin trigger 0) $display («%d mismatched vectors : Simulation failed !»,nummismatches); else $display («Simulation passed !»); $finish; end endmodule module freq_dev_vlg_vec_tst(); // constants // general purpose registers reg input; // wires wire output; wire sampler; // assign statements (if any) freq_dev i1 ( // port map — connection between master ports and signals/registers .input (input), .output (output) ); // input always begin input = 1’b0; input =# 25000 1’b1; # 25000; end freq_dev_vlg_sample_tst tb_sample ( .input(input), .sampler_tx(sampler) ); freq_dev_vlg_check_tst tb_out( .output(output), .sampler_rx(sampler) ); endmodule

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You cannot have an input called input — it is a reserved word in verilog.

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