Verilog constant driver error

I’m having a problem with Error 10028 and Error 10029 when i try and compile this in Quartus. I am using Quartus 2 Verilog HDL program language. I also receive this error but I’m hoping when what I’m doing wrong is fixed it will go away… 

quartus 2 internal error

Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/vrfx_sgate.cpp, Line: 1785 

oterm == clk 

Stack Trace: 

0x190c: thr_thread_var_get + 0xc (ccl_thr) 

End-trace 

Quartus II Version 9.1 Build 350 03/24/2010 SJ Web Edition 

Service Pack Installed: 2 

These are two separate always (AT) statements, There is more code telling what should happen when each of these states occur but I’ll leave that out for now. I just don’t quiet understand why I’m getting the errors I’m getting. The only coding background I have is a college level Java class as well as a little Verilog coding exercises. 

But here are the errors I am receiving when I put in the following code: 

errors

Error (10028): Can’t resolve multiple constant drivers for net «state.AA» at controller2.v(60) 

Error (10029): Constant driver at controller2.v(35) 

Error (10028): Can’t resolve multiple constant drivers for net «state.AB» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.AC» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.AD» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.AE» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.AF» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.AG» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.AH» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.AI» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.AJ» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.A» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.B» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.C» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.D» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.E» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.F» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.G» at controller2.v(60) 

Error (10028): Can’t resolve multiple constant drivers for net «state.H» at controller2.v(60) 

Line 35 is the always (AT) (posedge enter) statement 

Line 60 is the always (AT) (posedge clk) statement 

code


/*
* Always (AT) statement that when the user presses enter, will change from 1 state to the next until it hits state "A",
* this continues on later. Cycle from states (AA to AJ) each time a certain pushbutton (enter) is pressed. Once all states have
* been cycled through, go to the start of the next set of states (A).
*
* input: enter, pushbutton using debouncer
* input: state, AA - AJ and A - N
*/
always (AT) (posedge enter) begin

endcase
end


code description

The way it works in my head is: It stays at state «AA» until I press enter, when I do it changes to the next state. Once it hits state «A» it uses a clock signal to begin the loop needed to change between stats. Any help with this would be appreciated. When I edit out each section the file compiles fine but when they are both there together I get this issue. 

PS: (AT) is actually the AT sign, but this forums syntax doesnt allow new people to post links and I guess it see’s any AT sign as a link…

Verilog constant driver error

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Hello to everyone, i am having a lot of trouble to work with state machines using verilog!

here is my code

module maquina_irig ( clk_mi, rstn_mi, zero_mi, um_mi, p_mi, dez_mi, ts_mi, sinal_mi ); input clk_mi; // 20mhz from top input rstn_mi; // reset from top input zero_mi; // sinais irig com temporizacao input um_mi; input p_mi; input dez_mi; input ts_mi; // timestamp output sinal_mi; //sinal de saida wire ts_mi; reg sinal_mi; reg current_state, next_state; parameter idle = 0, send_p = 1, seconds =2; always @ (posedge clk_mi or negedge rstn_mi) if (

rstn_mi) begin current_state I am having those errors

Error (10028): Can’t resolve multiple constant drivers for net «next_state» at maquina_irig.v(61) Error (10029): Constant driver at maquina_irig.v(41) Error (10028): Can’t resolve multiple constant drivers for net «next_state» at maquina_irig.v(61) Error (10028): Can’t resolve multiple constant drivers for net «next_state» at maquina_irig.v(61) Any light in this darkness i am ? Thanks for the help..

Also if someone happens to know of any material about this subject i would be really thankful!

Источник

Verilog constant driver error

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• Re: Can’t resolve multiple constant drivers?

Can’t resolve multiple constant drivers?

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Hi, ive been trying to compile the code below in quartus II v9.0 and i get the following error message Error (10028): Can’t resolve multiple constant drivers for net «LSD_SEG[0]» at KEYBOARD.VHD(385)

ive tried to solve this since friday, now im out of options. the problem here is, i assign values to MSD_SEG & LSD_SEG from 3 different processes and quartus doesnt like that. i tried combining processes but only the push buttons (PB1 and PB2) are working and the keyboard isnt. The code compiles fine in Maxplus II but the thing is, Maxplus II doesnt support EP2C20F484CN FPGA (Cyclone II development board DE1). pls help

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I can´t find the signal LSD_SEG in the code you posted.

But one of the rules of VHDL is that you cannot assign a signal in more than one place. This error is a result of you assigning a value to the specified signal in more than one place.

Check that you are not assigning this signal outside of a process and inside, or in two or more different processes or in two or more different places outside of a process.

Right clicking on the warning in Quartus and clicking help, should help you to understand why you get this error.

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I can´t find the signal LSD_SEG in the code you posted.

But one of the rules of VHDL is that you cannot assign a signal in more than one place. This error is a result of you assigning a value to the specified signal in more than one place.

Check that you are not assigning this signal outside of a process and inside, or in two or more different processes or in two or more different places outside of a process.

Right clicking on the warning in Quartus and clicking help, should help you to understand why you get this error.

My bad, the signals are LSD_7SEG & MSD_7SEG. That’s exactly what my problem is, im assigning a signal in more than one place. hw can i not do that and still achieve the desired results?

Thanx for quick response

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I’m not a real VHDl expert, but as far as I know is the «‘EVENT» only allowed for single bits.

‘EVENT on vector is not syntheziable. Why not using a PROCESS with a sensitivity list ?

Your assign values to MSD_7SEG and LSD_7SEG in three different processes. That causes the multiple driver error. You have to combine the processes to one. Additinonal you have two wait statements in one process, which is also not allowed.

At pletz, ive already changed that «event» part, thank you. I tried combining the processes. it compiles but doesnt work as it should. this code works superbly on the UP2 board. Can you show me exactly to combine the processes?

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Both verilog and VHDL only allow you to write to a signal from a single process.

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I tried combining the processes. it compiles but doesnt work as it should.

Sounds plausible. Combining the processes creates legal VHDl semantic, but not necessarily intended behaviour. The basic problem is, that you have to resolve the conflicting assignments logically. Whatever code you write, you have to know which of the multiple signal assignments should be in effect at different times. The design compiler will resolve the conflict only based on code placement. The last assignment wins.

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Sounds plausible. Combining the processes creates legal VHDl semantic, but not necessarily intended behaviour. The basic problem is, that you have to resolve the conflicting assignments logically. Whatever code you write, you have to know which of the multiple signal assignments should be in effect at different times. The design compiler will resolve the conflict only based on code placement. The last assignment wins.

I even tried using a multiplexer, both parts work but the one part is not displayed. for example, when i press the push button, 7 seg displays, display the contents stored for push button event but when i release it, last key pressed on the keyboard is displayed and thats not how it should work.

This is how it should work:

1. when i press a key on the keyboard, the contents associated with that key should be displayed and stay displayed.

2. when i press the push button, the contents associated with push button counter should be displayed and stay displayed.

3. (1) and (2) work fine independently, problem arises when i put them in a single file.

im new to vhdl and like i said, i’ve been trying to resolve this since friday and this project is due tomorrow. please help pls. i’ve attached a more readable code, pls help me correct it.:confused:

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Aside from multiple drivers, a huge problem you’re going to have is your clocking scheme.

You have generated your own clock using logic, and you are clocking other processes with that logic generated clock. In FPGAs, this is a big problem as it can cause all sorts of timing issues. Its much better to generate an enable for registers that are clocked from the source clock.

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Aside from multiple drivers, a huge problem you’re going to have is your clocking scheme.

You have generated your own clock using logic, and you are clocking other processes with that logic generated clock. In FPGAs, this is a big problem as it can cause all sorts of timing issues. Its much better to generate an enable for registers that are clocked from the source clock.

Hi tricky, can you pls help with some form of example? the cyclone II DE1 board didnt have any timing issues so i didnt think that would be a problem. The clock that ive generated is only used by the push button process (i think), coz the keyboard has clock conneted to it already.

I been with vhdl for 2 weeks now, so everything is just new to me. 🙁

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No Problem. with VHDL you can write whatever VHDL you want and have it simulate fine, but if it isnt written with recommended coding styles you cant guarantee that the synthesised firmware will work.

Did you set any timing requirements when you say it doesnt throw any warnings?

For all VHDL you are going to synthesize, the recommended style for a clock process (to generate registers) is this:

reg_proc : process(clk, reset) begin if reset = ‘1’ then —asynchronous reset elsif rising_edge(clk) then —registered statements go here if enable = ‘1’ then —register with enable statements go here end if; end if; end process;

Using wait statements in process is allowed, but not a common form. It can be safer to use the rising_edge(clk) method above, because more people will have seen it and I know all synthesisors will work with it. Use wait statements to your hearts content in testbenches (where they can be very useful for creating bus functional models).

As you are new to VHDL, can I also recommend you stop using std_logic_arith and std_logic_signed/unsigned now. They are non-standard packages. They have become a bit of a defacto standard. The real IEEE standard is numeric_std, which I recommend using over the other 2 packages. it allows you to do signed and unsigned arithmatic in the same file (the other method does not) and with proper typing and much better named functions it makes more sense. It is also compatible with the new standardised fixed point libraries for doing really easy fixed point maths.

Another thing to remember is that internal ports on entites (ie. ones that dont connect to pins) can be any type you want — so use integers/boolean/enummerated types to make your code much more readable.

Any other questions, please ask away.

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No Problem. with VHDL you can write whatever VHDL you want and have it simulate fine, but if it isnt written with recommended coding styles you cant guarantee that the synthesised firmware will work.

Did you set any timing requirements when you say it doesnt throw any warnings?

For all VHDL you are going to synthesize, the recommended style for a clock process (to generate registers) is this:

reg_proc : process(clk, reset) begin if reset = ‘1’ then —asynchronous reset elsif rising_edge(clk) then —registered statements go here if enable = ‘1’ then —register with enable statements go here end if; end if; end process;

Using wait statements in process is allowed, but not a common form. It can be safer to use the rising_edge(clk) method above, because more people will have seen it and I know all synthesisors will work with it. Use wait statements to your hearts content in testbenches (where they can be very useful for creating bus functional models).

As you are new to VHDL, can I also recommend you stop using std_logic_arith and std_logic_signed/unsigned now. They are non-standard packages. They have become a bit of a defacto standard. The real IEEE standard is numeric_std, which I recommend using over the other 2 packages. it allows you to do signed and unsigned arithmatic in the same file (the other method does not) and with proper typing and much better named functions it makes more sense. It is also compatible with the new standardised fixed point libraries for doing really easy fixed point maths.

Another thing to remember is that internal ports on entites (ie. ones that dont connect to pins) can be any type you want — so use integers/boolean/enummerated types to make your code much more readable.

Any other questions, please ask away.

Ohk Tricky thanx. i get the timing warnings but they dont matter for now because ive tested both keyboard process and push button processes independently and they work fine. the problem is to get them to work together. can you please help me with that? look at the code and try to see what can be done to resolve the issue. pls try to compile it, ull see what im talking about.

Источник

Ошибка «Множественные постоянные драйверы» Verilog с Quartus Prime

Я работаю над разработкой конечного автомата в Verilog для представления стека. Модуль выглядит следующим образом:

OF_Err и UF_Err — индикаторы ошибок переполнения и потери значимости соответственно.

Однако при компиляции проекта я получаю следующие ошибки:

Error (10028): Can’t resolve multiple constant drivers for net «OF_Err» at state_machine.v(59) Error (10029): Constant driver at state_machine.v(10) Error (10028): Can’t resolve multiple constant drivers for net «UF_Err» at state_machine.v(59)

Они появились только после того, как я добавил строки с комментариями. Я хочу сбросить индикаторы переполнения и опустошения при сбросе конечного автомата, но я не могу сделать это так, как у меня есть. Как мне это сделать?

(Если он имеет какое-либо значение, это должно выполняться на Altera DE2-115).

3 ответа

Как уже отмечали другие, OF_Err и UF_Err были драйверами двумя всегда блоками, что недопустимо для синтеза. Я рекомендую создать две дополнительные переменные of_Err и uf_Err , как предложил Арвинд. Однако я рекомендую оставить OF_Err и UF_Err как флоп.

if (Enable) в комбинационном блоке подразумевает Y , c и *_Err как чувствительные к уровню защелки. Я очень сомневаюсь, что это то, что вы хотели. Я рекомендую переместить if (Enable) в синхронный всегда блок и сохранить комбинационную логику как чисто комбинационную.

c — простое присваивание, поэтому было бы целесообразнее использовать его как провод, а не регистр с простым оператором присваивания. Это может быть комбинационный блок, но я предпочитаю отделить комбинационный ввод от вывода.

Вы правильно использовали @(s, y, Enable) , однако @* или синоним @(*) рекомендуется для комбинационного блока. @* — это список автоматической чувствительности, который избавляет вас от набора текста, обслуживания и исключает риск забыть сигнал.

Поскольку OF_Err и UF_ERR управляются несколькими блоками always.

Рег должен управляться только одним всегда блоком. И если он имеет несколько драйверов по дизайну, то это должен быть провод.

Вот ваш измененный код.

В двух блоках always вы присвоили значения OF_Err и UF_Err . Это причина того, что он показывает множественную ошибку постоянного драйвера.

Источник

module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output reg OF_Err = 0, UF_Err = 0;
reg [2:0] y, Y;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;

always @(s, y, Enable)
    if (Enable)
        begin
            case (y)
                A: if (s == 3'b000) Y = B;
                    else
                        begin
                            Y = A;
                            UF_Err = 1;
                        end

                B: if (s == 3'b000) Y = C;
                    else if (s == 3'b001) Y = A;
                    else
                        begin
                            Y = B;
                            UF_Err = 1;
                        end

                C: if (s == 3'b000) Y = D;
                    else if (s == 3'b100) Y = C;
                    else Y = B;

                D: if (s == 3'b000) Y = E;
                    else if (s == 3'b100) Y = D;
                    else Y = C;

                E: if (s == 3'b000)
                        begin
                            Y = E;
                            OF_Err = 1;
                        end
                    else if (s == 3'b100) Y = E;
                    else Y = D;

                default: Y = 3'bxxx;
            endcase

            c[1] = y[1];
            c[0] = y[0];
        end

always @(negedge Resetn, posedge Clock)
    begin
        if (Resetn == 0)
            begin
                y <= A;
                OF_Err = 0; //Problem
                UF_Err = 0; //Problem
            end
        else y <= Y;
    end

3 Answers

module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
   input [2:0] s;
   input Enable, Clock, Resetn;
   output reg [1:0] c;
   output OF_Err, UF_Err;         //modified
   reg [2:0] y, Y;
   reg of_Err, uf_Err;              //added
   parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E =3'b100;

   always @*
   begin
        if (Enable)
        begin
            case (y)
                A: if (s == 3'b000)
                       Y = B;
                   else
                   begin
                       Y = A;
                       uf_Err = 1;      //modified
                   end

               B: if (s == 3'b000)
                    Y = C;
                  else if (s == 3'b001)
                    Y = A;
                  else
                  begin
                    Y = B;
                    uf_Err = 1;     //modified
                  end

            C: if (s == 3'b000)
                    Y = D;
                else if (s == 3'b100)
                    Y = C;
                else 
                    Y = B;

            D: if (s == 3'b000) 
                Y = E;
                else if (s == 3'b100) 
                    Y = D;
                else Y = C;

            E: if (s == 3'b000)
                    begin
                        Y = E;
                        of_Err = 1;         //modified
                    end
                else if (s == 3'b100) Y = E;
                else Y = D;

            default: Y = 3'bxxx;
        endcase

        c[1] = y[1];
        c[0] = y[0];
    end
       else
       begin
    //write the condition if the Enable signal is not high.I guess you're trying to synthesize
       end

   end

always @(negedge Resetn, posedge Clock)
begin
    if (Resetn == 0)
        begin
            y <= A;
        //    OF_Err = 0; //Problem
        //    UF_Err = 0; //Problem
        end
    else y <= Y;
end

assign OF_Err = !Resetn? of_Err : 1'b0;     //added
assign UF_Err = !Resetn? uf_Err : 1'b0;     //added

 endmodule

module state_machine (s, Enable, Clock, Resetn, c, OF_Err, UF_Err);
input [2:0] s;
input Enable, Clock, Resetn;
output reg [1:0] c;
output reg OF_Err = 0, UF_Err = 0;
reg [2:0] y, Y;
parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100;

always @(s, y, Enable, negedge reset)
begin
  if (!reset)
  begin
    OF_Err = 0; //Problem
    UF_Err = 0; //Problem
  end
  else 
  begin 
    if (Enable)
    begin
      case (y)
      A: if (s == 3'b000) Y = B;
         else
         begin
           Y = A;
           UF_Err = 1;
         end
      B: if (s == 3'b000) Y = C;
         else if (s == 3'b001) Y = A;
         else
         begin
           Y = B;
           UF_Err = 1;
         end
      C: if (s == 3'b000) Y = D;
         else if (s == 3'b100) Y = C;
         else Y = B;
      D: if (s == 3'b000) Y = E;
         else if (s == 3'b100) Y = D;
         else Y = C;
      E: if (s == 3'b000)
         begin
           Y = E;
           OF_Err = 1;
         end
         else if (s == 3'b100) Y = E;
         else Y = D;
      default: Y = 3'bxxx;
      endcase

      c[1] = y[1];
      c[0] = y[0];
    end
  end 
end

always @(negedge Resetn, posedge Clock)
begin
  if(Resetn == 0)
    y <= A;
  else 
    y <= Y;
end

always @*
begin
  of_Err = OF_Err; // <-- default values
  uf_Err = UF_Err;

  case (y)
    // ... your original case code with OF_Err/UF_Err renamed to of_Err/uf_Err
  endcase
end

always @(posedge Clock, negedge Resetn) // style difference, I prefer the clock to be first
begin
  if (Resetn == 1'b0)
  begin
    y <= A;
    OF_Err <= 1'b0;
    UF_Err <= 1'b0;
  end
  else if (Enable)
  begin
    y <= Y;
    OF_Err <= of_Err;
    UF_Err <= uf_Err;
  end
end
assign c[1:0] = y[1:0];